1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stddef.h>
8 #include <string.h>
9 #include <common/debug.h>
10 #include <lib/bakery_lock.h>
11 #include <lib/mmio.h>
12 #include <mt_lp_rm.h>
13 #include <mt_spm.h>
14 #include <mt_spm_cond.h>
15 #include <mt_spm_conservation.h>
16 #include <mt_spm_constraint.h>
17 #include <mt_spm_idle.h>
18 #include <mt_spm_internal.h>
19 #include <mt_spm_pmic_wrap.h>
20 #include <mt_spm_rc_internal.h>
21 #include <mt_spm_reg.h>
22 #include <mt_spm_resource_req.h>
23 #include <mt_spm_suspend.h>
24 #include <mtk_plat_common.h>
25 #include <plat_mtk_lpm.h>
26 #include <plat_pm.h>
27 #include <platform_def.h>
28 #include <sleep_def.h>
29
30 #ifdef MT_SPM_USING_BAKERY_LOCK
31 DEFINE_BAKERY_LOCK(spm_lock);
32 #define plat_spm_lock_init() bakery_lock_init(&spm_lock)
33 #else
34 spinlock_t spm_lock;
35 #define plat_spm_lock_init()
36 #endif
37
38 /* CLK_SCP_CFG_0 */
39 #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x264)
40 #define SPM_CK_CONTROL_EN 0x7FF
41
42 struct mt_resource_constraint plat_constraint_bus26m = {
43 .is_valid = spm_is_valid_rc_bus26m,
44 .update = spm_update_rc_bus26m,
45 .allow = spm_allow_rc_bus26m,
46 .run = spm_run_rc_bus26m,
47 .reset = spm_reset_rc_bus26m,
48 };
49
50 struct mt_resource_constraint plat_constraint_syspll = {
51 .is_valid = spm_is_valid_rc_syspll,
52 .update = spm_update_rc_syspll,
53 .allow = spm_allow_rc_syspll,
54 .run = spm_run_rc_syspll,
55 .reset = spm_reset_rc_syspll,
56 };
57
58 struct mt_resource_constraint plat_constraint_dram = {
59 .is_valid = spm_is_valid_rc_dram,
60 .update = spm_update_rc_dram,
61 .allow = spm_allow_rc_dram,
62 .run = spm_run_rc_dram,
63 .reset = spm_reset_rc_dram,
64 };
65
66 struct mt_resource_constraint plat_constraint_cpu = {
67 .is_valid = spm_is_valid_rc_cpu_buck_ldo,
68 .update = NULL,
69 .allow = spm_allow_rc_cpu_buck_ldo,
70 .run = spm_run_rc_cpu_buck_ldo,
71 .reset = spm_reset_rc_cpu_buck_ldo,
72 };
73
74 struct mt_resource_constraint *plat_constraints[] = {
75 &plat_constraint_bus26m,
76 &plat_constraint_syspll,
77 &plat_constraint_dram,
78 &plat_constraint_cpu,
79 NULL,
80 };
81
82 struct mt_resource_manager plat_mt8195_rm = {
83 .update = mt_spm_cond_update,
84 .consts = plat_constraints,
85 };
86
spm_boot_init(void)87 void spm_boot_init(void)
88 {
89 NOTICE("MT8195 %s\n", __func__);
90 /* switch ck_off/axi_26m control to SPM */
91 mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
92
93 plat_spm_lock_init();
94 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
95 mt_lp_rm_register(&plat_mt8195_rm);
96 mt_spm_idle_generic_init();
97 mt_spm_suspend_init();
98 }
99