1#
2# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8TZDRAM_BASE				:= 0xFF800000
9$(eval $(call add_define,TZDRAM_BASE))
10
11ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT	:= 1
12$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
13
14PLATFORM_CLUSTER_COUNT			:= 2
15$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
16
17PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
18$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
19
20MAX_XLAT_TABLES				:= 10
21$(eval $(call add_define,MAX_XLAT_TABLES))
22
23MAX_MMAP_REGIONS			:= 16
24$(eval $(call add_define,MAX_MMAP_REGIONS))
25
26ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING	:= 1
27
28PLAT_INCLUDES		+=	-Iplat/nvidia/tegra/include/t210		\
29				-I${SOC_DIR}/drivers/se
30
31BL31_SOURCES		+=	${TEGRA_GICv2_SOURCES}				\
32				drivers/ti/uart/aarch64/16550_console.S		\
33				lib/cpus/aarch64/cortex_a53.S			\
34				lib/cpus/aarch64/cortex_a57.S			\
35				${TEGRA_DRIVERS}/bpmp/bpmp.c			\
36				${TEGRA_DRIVERS}/flowctrl/flowctrl.c		\
37				${TEGRA_DRIVERS}/memctrl/memctrl_v1.c		\
38				${TEGRA_DRIVERS}/pmc/pmc.c			\
39				${SOC_DIR}/plat_psci_handlers.c			\
40				${SOC_DIR}/plat_setup.c				\
41				${SOC_DIR}/drivers/se/security_engine.c		\
42				${SOC_DIR}/plat_secondary.c			\
43				${SOC_DIR}/plat_sip_calls.c
44
45# Enable workarounds for selected Cortex-A57 erratas.
46A57_DISABLE_NON_TEMPORAL_HINT	:=	1
47ERRATA_A57_826974		:=	1
48ERRATA_A57_826977		:=	1
49ERRATA_A57_828024		:=	1
50ERRATA_A57_833471		:=	1
51
52# Enable workarounds for selected Cortex-A53 erratas.
53A53_DISABLE_NON_TEMPORAL_HINT	:=	1
54ERRATA_A53_826319		:=	1
55ERRATA_A53_836870		:=	1
56ERRATA_A53_855873		:=	1
57
58# Skip L1 $ flush when powering down Cortex-A57 CPUs
59SKIP_A57_L1_FLUSH_PWR_DWN	:=	1
60
61# Enable higher performance Non-cacheable load forwarding
62A57_ENABLE_NONCACHEABLE_LOAD_FWD	:=	1
63