1 /* 2 * Copyright 2018-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_DEF_H 8 #define PLAT_DEF_H 9 10 #include <arch.h> 11 /* Required without TBBR. 12 * To include the defines for DDR PHY 13 * Images. 14 */ 15 #include <tbbr_img_def.h> 16 17 #include <policy.h> 18 #include <soc.h> 19 20 #define NXP_SPD_EEPROM0 0x51 21 22 #define NXP_SYSCLK_FREQ 100000000 23 #define NXP_DDRCLK_FREQ 100000000 24 25 /* UART related definition */ 26 #define NXP_CONSOLE_ADDR NXP_UART_ADDR 27 #define NXP_CONSOLE_BAUDRATE 115200 28 29 /* Size of cacheable stacks */ 30 #if defined(IMAGE_BL2) 31 #if defined(TRUSTED_BOARD_BOOT) 32 #define PLATFORM_STACK_SIZE 0x2000 33 #else 34 #define PLATFORM_STACK_SIZE 0x1000 35 #endif 36 #elif defined(IMAGE_BL31) 37 #define PLATFORM_STACK_SIZE 0x1000 38 #endif 39 40 /* SD block buffer */ 41 #define NXP_SD_BLOCK_BUF_SIZE (0x00100000) 42 #define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000) 43 44 #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 45 46 /* IO defines as needed by IO driver framework */ 47 #define MAX_IO_DEVICES U(3) 48 #define MAX_IO_BLOCK_DEVICES U(1) 49 #define MAX_IO_HANDLES U(4) 50 51 /* 52 * FIP image defines - Offset at which FIP Image would be present 53 * Image would include Bl31 , Bl33 and Bl32 (optional) 54 */ 55 #ifdef POLICY_FUSE_PROVISION 56 #define MAX_FIP_DEVICES U(2) 57 #endif 58 59 #ifndef MAX_FIP_DEVICES 60 #define MAX_FIP_DEVICES U(1) 61 #endif 62 63 /* 64 * ID of the secure physical generic timer interrupt used by the BL32. 65 */ 66 #define BL32_IRQ_SEC_PHY_TIMER 29 67 68 /* 69 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 70 * terminology. On a GICv2 system or mode, the lists will be merged and treated 71 * as Group 0 interrupts. 72 */ 73 #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 74 INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75 GIC_INTR_CFG_LEVEL) 76 77 #define PLAT_LS_G0_IRQ_PROPS(grp) 78 79 #endif 80