1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <libfdt.h>
11
12 #include <platform_def.h>
13
14 #include <arch_helpers.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <common/desc_image_load.h>
18 #include <common/fdt_fixup.h>
19 #include <lib/optee_utils.h>
20 #include <lib/utils.h>
21 #include <plat/common/platform.h>
22
23 #include "qemu_private.h"
24
25
26 /* Data structure which holds the extents of the trusted SRAM for BL2 */
27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
28
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)29 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
30 u_register_t arg2, u_register_t arg3)
31 {
32 meminfo_t *mem_layout = (void *)arg1;
33
34 /* Initialize the console to provide early debug support */
35 qemu_console_init();
36
37 /* Setup the BL2 memory layout */
38 bl2_tzram_layout = *mem_layout;
39
40 plat_qemu_io_setup();
41 }
42
security_setup(void)43 static void security_setup(void)
44 {
45 /*
46 * This is where a TrustZone address space controller and other
47 * security related peripherals, would be configured.
48 */
49 }
50
update_dt(void)51 static void update_dt(void)
52 {
53 int ret;
54 void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
55
56 ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
57 if (ret < 0) {
58 ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
59 return;
60 }
61
62 if (dt_add_psci_node(fdt)) {
63 ERROR("Failed to add PSCI Device Tree node\n");
64 return;
65 }
66
67 if (dt_add_psci_cpu_enable_methods(fdt)) {
68 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
69 return;
70 }
71
72 ret = fdt_pack(fdt);
73 if (ret < 0)
74 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
75 }
76
bl2_platform_setup(void)77 void bl2_platform_setup(void)
78 {
79 security_setup();
80 update_dt();
81
82 /* TODO Initialize timer */
83 }
84
85 #ifdef __aarch64__
86 #define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
87 #else
88 #define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
89 #endif
90
bl2_plat_arch_setup(void)91 void bl2_plat_arch_setup(void)
92 {
93 QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
94 bl2_tzram_layout.total_size,
95 BL_CODE_BASE, BL_CODE_END,
96 BL_RO_DATA_BASE, BL_RO_DATA_END,
97 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
98 }
99
100 /*******************************************************************************
101 * Gets SPSR for BL32 entry
102 ******************************************************************************/
qemu_get_spsr_for_bl32_entry(void)103 static uint32_t qemu_get_spsr_for_bl32_entry(void)
104 {
105 #ifdef __aarch64__
106 /*
107 * The Secure Payload Dispatcher service is responsible for
108 * setting the SPSR prior to entry into the BL3-2 image.
109 */
110 return 0;
111 #else
112 return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
113 DISABLE_ALL_EXCEPTIONS);
114 #endif
115 }
116
117 /*******************************************************************************
118 * Gets SPSR for BL33 entry
119 ******************************************************************************/
qemu_get_spsr_for_bl33_entry(void)120 static uint32_t qemu_get_spsr_for_bl33_entry(void)
121 {
122 uint32_t spsr;
123 #ifdef __aarch64__
124 unsigned int mode;
125
126 /* Figure out what mode we enter the non-secure world in */
127 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
128
129 /*
130 * TODO: Consider the possibility of specifying the SPSR in
131 * the FIP ToC and allowing the platform to have a say as
132 * well.
133 */
134 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
135 #else
136 spsr = SPSR_MODE32(MODE32_svc,
137 plat_get_ns_image_entrypoint() & 0x1,
138 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
139 #endif
140 return spsr;
141 }
142
qemu_bl2_handle_post_image_load(unsigned int image_id)143 static int qemu_bl2_handle_post_image_load(unsigned int image_id)
144 {
145 int err = 0;
146 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
147 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) || defined(SPMC_OPTEE)
148 bl_mem_params_node_t *pager_mem_params = NULL;
149 bl_mem_params_node_t *paged_mem_params = NULL;
150 #endif
151 #if defined(SPD_spmd)
152 unsigned int mode_rw = MODE_RW_64;
153 uint64_t pagable_part = 0;
154 #endif
155
156 assert(bl_mem_params);
157
158 switch (image_id) {
159 case BL32_IMAGE_ID:
160 #if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE) || defined(SPMC_OPTEE)
161 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
162 assert(pager_mem_params);
163
164 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
165 assert(paged_mem_params);
166
167 err = parse_optee_header(&bl_mem_params->ep_info,
168 &pager_mem_params->image_info,
169 &paged_mem_params->image_info);
170 if (err != 0) {
171 WARN("OPTEE header parse error.\n");
172 }
173 #if defined(SPD_spmd)
174 mode_rw = bl_mem_params->ep_info.args.arg0;
175 pagable_part = bl_mem_params->ep_info.args.arg1;
176 #endif
177 #endif
178
179 #if defined(SPD_spmd)
180 bl_mem_params->ep_info.args.arg0 = ARM_PRELOADED_DTB_BASE;
181 bl_mem_params->ep_info.args.arg1 = pagable_part;
182 bl_mem_params->ep_info.args.arg2 = mode_rw;
183 bl_mem_params->ep_info.args.arg3 = 0;
184 #elif defined(SPD_opteed)
185 /*
186 * OP-TEE expect to receive DTB address in x2.
187 * This will be copied into x2 by dispatcher.
188 */
189 bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
190 #elif defined(AARCH32_SP_OPTEE)
191 bl_mem_params->ep_info.args.arg0 =
192 bl_mem_params->ep_info.args.arg1;
193 bl_mem_params->ep_info.args.arg1 = 0;
194 bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
195 bl_mem_params->ep_info.args.arg3 = 0;
196 #endif
197 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
198 break;
199
200 case BL33_IMAGE_ID:
201 #ifdef AARCH32_SP_OPTEE
202 /* AArch32 only core: OP-TEE expects NSec EP in register LR */
203 pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
204 assert(pager_mem_params);
205 pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
206 #endif
207
208 #if ARM_LINUX_KERNEL_AS_BL33
209 /*
210 * According to the file ``Documentation/arm64/booting.txt`` of
211 * the Linux kernel tree, Linux expects the physical address of
212 * the device tree blob (DTB) in x0, while x1-x3 are reserved
213 * for future use and must be 0.
214 */
215 bl_mem_params->ep_info.args.arg0 =
216 (u_register_t)ARM_PRELOADED_DTB_BASE;
217 bl_mem_params->ep_info.args.arg1 = 0U;
218 bl_mem_params->ep_info.args.arg2 = 0U;
219 bl_mem_params->ep_info.args.arg3 = 0U;
220 #else
221 /* BL33 expects to receive the primary CPU MPID (through r0) */
222 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
223 #endif
224
225 bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
226 break;
227 default:
228 /* Do nothing in default case */
229 break;
230 }
231
232 return err;
233 }
234
235 /*******************************************************************************
236 * This function can be used by the platforms to update/use image
237 * information for given `image_id`.
238 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)239 int bl2_plat_handle_post_image_load(unsigned int image_id)
240 {
241 return qemu_bl2_handle_post_image_load(image_id);
242 }
243
plat_get_ns_image_entrypoint(void)244 uintptr_t plat_get_ns_image_entrypoint(void)
245 {
246 return NS_IMAGE_OFFSET;
247 }
248