1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #define FIP_IMAGE_NAME "fip" 29 #define METADATA_PART_1 "metadata1" 30 #define METADATA_PART_2 "metadata2" 31 32 #define STM32MP_PRIMARY_CPU U(0x0) 33 #define STM32MP_SECONDARY_CPU U(0x1) 34 35 #define PLATFORM_CLUSTER_COUNT U(1) 36 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 37 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 38 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 39 PLATFORM_CLUSTER0_CORE_COUNT) 40 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 41 42 #define MAX_IO_DEVICES U(4) 43 #define MAX_IO_HANDLES U(4) 44 #define MAX_IO_BLOCK_DEVICES U(1) 45 #define MAX_IO_MTD_DEVICES U(1) 46 47 /******************************************************************************* 48 * BL2 specific defines. 49 ******************************************************************************/ 50 /* 51 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 52 * size plus a little space for growth. 53 */ 54 #define BL2_BASE STM32MP_BL2_BASE 55 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 56 STM32MP_BL2_SIZE) 57 58 #define BL2_RO_BASE STM32MP_BL2_RO_BASE 59 #define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \ 60 STM32MP_BL2_RO_SIZE) 61 62 #define BL2_RW_BASE STM32MP_BL2_RW_BASE 63 #define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \ 64 STM32MP_BL2_RW_SIZE) 65 /******************************************************************************* 66 * BL32 specific defines. 67 ******************************************************************************/ 68 #if defined(IMAGE_BL32) 69 #if ENABLE_PIE 70 #define BL32_BASE 0 71 #define BL32_LIMIT STM32MP_BL32_SIZE 72 #else 73 #define BL32_BASE STM32MP_BL32_BASE 74 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 75 STM32MP_BL32_SIZE) 76 #endif 77 #endif /* defined(IMAGE_BL32) */ 78 79 /******************************************************************************* 80 * BL33 specific defines. 81 ******************************************************************************/ 82 #define BL33_BASE STM32MP_BL33_BASE 83 84 /* 85 * Load address of BL33 for this platform port 86 */ 87 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 88 89 /* Needed by STM32CubeProgrammer support */ 90 #define DWL_BUFFER_SIZE U(0x01000000) 91 92 /* 93 * SSBL offset in case it's stored in eMMC boot partition. 94 * We can fix it to 256K because TF-A size can't be bigger than SRAM 95 */ 96 #define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000) 97 98 /******************************************************************************* 99 * DTB specific defines. 100 ******************************************************************************/ 101 #define DTB_BASE STM32MP_DTB_BASE 102 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 103 STM32MP_DTB_SIZE) 104 105 /******************************************************************************* 106 * Platform specific page table and MMU setup constants 107 ******************************************************************************/ 108 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 109 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 110 111 /******************************************************************************* 112 * Declarations and constants to access the mailboxes safely. Each mailbox is 113 * aligned on the biggest cache line size in the platform. This is known only 114 * to the platform as it might have a combination of integrated and external 115 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 116 * line at any cache level. They could belong to different cpus/clusters & 117 * get written while being protected by different locks causing corruption of 118 * a valid mailbox address. 119 ******************************************************************************/ 120 #define CACHE_WRITEBACK_SHIFT 6 121 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 122 123 /* 124 * Secure Interrupt: based on the standard ARM mapping 125 */ 126 #define ARM_IRQ_SEC_PHY_TIMER U(29) 127 128 #define ARM_IRQ_SEC_SGI_0 U(8) 129 #define ARM_IRQ_SEC_SGI_1 U(9) 130 #define ARM_IRQ_SEC_SGI_2 U(10) 131 #define ARM_IRQ_SEC_SGI_3 U(11) 132 #define ARM_IRQ_SEC_SGI_4 U(12) 133 #define ARM_IRQ_SEC_SGI_5 U(13) 134 #define ARM_IRQ_SEC_SGI_6 U(14) 135 #define ARM_IRQ_SEC_SGI_7 U(15) 136 137 #define STM32MP1_IRQ_TZC400 U(36) 138 #define STM32MP1_IRQ_TAMPSERRS U(229) 139 #define STM32MP1_IRQ_AXIERRIRQ U(244) 140 141 /* 142 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 143 * terminology. On a GICv2 system or mode, the lists will be merged and treated 144 * as Group 0 interrupts. 145 */ 146 #define PLATFORM_G1S_PROPS(grp) \ 147 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 148 GIC_HIGHEST_SEC_PRIORITY, \ 149 grp, GIC_INTR_CFG_LEVEL), \ 150 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 151 GIC_HIGHEST_SEC_PRIORITY, \ 152 grp, GIC_INTR_CFG_LEVEL), \ 153 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 154 GIC_HIGHEST_SEC_PRIORITY, \ 155 grp, GIC_INTR_CFG_LEVEL), \ 156 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 157 GIC_HIGHEST_SEC_PRIORITY, \ 158 grp, GIC_INTR_CFG_EDGE), \ 159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 160 GIC_HIGHEST_SEC_PRIORITY, \ 161 grp, GIC_INTR_CFG_EDGE), \ 162 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 163 GIC_HIGHEST_SEC_PRIORITY, \ 164 grp, GIC_INTR_CFG_EDGE), \ 165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 166 GIC_HIGHEST_SEC_PRIORITY, \ 167 grp, GIC_INTR_CFG_EDGE), \ 168 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 169 GIC_HIGHEST_SEC_PRIORITY, \ 170 grp, GIC_INTR_CFG_EDGE), \ 171 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 172 GIC_HIGHEST_SEC_PRIORITY, \ 173 grp, GIC_INTR_CFG_EDGE) 174 175 #define PLATFORM_G0_PROPS(grp) \ 176 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 177 GIC_HIGHEST_SEC_PRIORITY, \ 178 grp, GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 180 GIC_HIGHEST_SEC_PRIORITY, \ 181 grp, GIC_INTR_CFG_EDGE) 182 183 /* 184 * Power 185 */ 186 #define PLAT_MAX_PWR_LVL U(1) 187 188 /* Local power state for power domains in Run state. */ 189 #define ARM_LOCAL_STATE_RUN U(0) 190 /* Local power state for retention. Valid only for CPU power domains */ 191 #define ARM_LOCAL_STATE_RET U(1) 192 /* Local power state for power-down. Valid for CPU and cluster power domains */ 193 #define ARM_LOCAL_STATE_OFF U(2) 194 /* 195 * This macro defines the deepest retention state possible. 196 * A higher state id will represent an invalid or a power down state. 197 */ 198 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 199 /* 200 * This macro defines the deepest power down states possible. Any state ID 201 * higher than this is invalid. 202 */ 203 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 204 205 /******************************************************************************* 206 * Size of the per-cpu data in bytes that should be reserved in the generic 207 * per-cpu data structure for the FVP port. 208 ******************************************************************************/ 209 #define PLAT_PCPU_DATA_SIZE 2 210 211 /******************************************************************************* 212 * Number of parallel entry slots in SMT SCMI server entry context. For this 213 * platform, SCMI server is reached through SMC only, hence the number of 214 * entry slots. 215 ******************************************************************************/ 216 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 217 218 #endif /* PLATFORM_DEF_H */ 219