1 /* 2 * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BOARD_DEF_H 8 #define BOARD_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /* The ports must be in order and contiguous */ 13 #define K3_CLUSTER0_CORE_COUNT U(4) 14 #define K3_CLUSTER1_CORE_COUNT U(0) 15 #define K3_CLUSTER2_CORE_COUNT U(0) 16 #define K3_CLUSTER3_CORE_COUNT U(0) 17 18 /* 19 * This RAM will be used for the bootloader including code, bss, and stacks. 20 * It may need to be increased if BL31 grows in size. 21 * Current computation assumes data structures necessary for GIC and ARM for 22 * a single cluster of 4 processor. 23 * 24 * The link addresses are determined by SEC_SRAM_BASE + offset. 25 * When ENABLE_PIE is set, the TF images can be loaded anywhere, so 26 * SEC_SRAM_BASE is really arbitrary. 27 * 28 * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that 29 * it matches to the physical address where BL31 is loaded, that is, 30 * SEC_SRAM_BASE should be the base address of the RAM region. 31 * 32 * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is 33 * defined as default for our platform. 34 */ 35 #define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ 36 #define SEC_SRAM_SIZE UL(0x00020000) /* 128k */ 37 38 #define PLAT_MAX_OFF_STATE U(2) 39 #define PLAT_MAX_RET_STATE U(1) 40 41 #define PLAT_PROC_START_ID U(32) 42 #define PLAT_PROC_DEVICE_START_ID U(135) 43 #define PLAT_CLUSTER_DEVICE_START_ID U(134) 44 45 #endif /* BOARD_DEF_H */ 46