1 /*
2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <errno.h>
11 #include <plat_arm.h>
12 #include <plat_private.h>
13 #include <bl31/bl31.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <drivers/arm/dcc.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/console.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables.h>
21 #include <plat/common/platform.h>
22 #include <versal_def.h>
23 #include <plat_private.h>
24 #include <plat_startup.h>
25 #include <pm_ipi.h>
26 #include "pm_client.h"
27 #include "pm_api_sys.h"
28
29 static entry_point_info_t bl32_image_ep_info;
30 static entry_point_info_t bl33_image_ep_info;
31
32 /*
33 * Return a pointer to the 'entry_point_info' structure of the next image for
34 * the security state specified. BL33 corresponds to the non-secure image type
35 * while BL32 corresponds to the secure image type. A NULL pointer is returned
36 * if the image does not exist.
37 */
bl31_plat_get_next_image_ep_info(uint32_t type)38 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
39 {
40 assert(sec_state_is_valid(type));
41
42 if (type == NON_SECURE) {
43 return &bl33_image_ep_info;
44 }
45
46 return &bl32_image_ep_info;
47 }
48
49 /*
50 * Set the build time defaults,if we can't find any config data.
51 */
bl31_set_default_config(void)52 static inline void bl31_set_default_config(void)
53 {
54 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
55 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
58 DISABLE_ALL_EXCEPTIONS);
59 }
60
61 /*
62 * Perform any BL31 specific platform actions. Here is an opportunity to copy
63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
64 * are lost (potentially). This needs to be done before the MMU is initialized
65 * so that the memory layout can be used while creating page tables.
66 */
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)67 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
68 u_register_t arg2, u_register_t arg3)
69 {
70 uint64_t atf_handoff_addr;
71 uint32_t payload[PAYLOAD_ARG_CNT], max_size = ATF_HANDOFF_PARAMS_MAX_SIZE;
72 enum pm_ret_status ret_status;
73 uint64_t addr[ATF_HANDOFF_PARAMS_MAX_SIZE];
74
75 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
76 static console_t versal_runtime_console;
77 /* Initialize the console to provide early debug support */
78 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE,
79 (uint32_t)VERSAL_UART_CLOCK,
80 (uint32_t)VERSAL_UART_BAUDRATE,
81 &versal_runtime_console);
82 if (rc == 0) {
83 panic();
84 }
85
86 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT |
87 CONSOLE_FLAG_RUNTIME));
88 } else if (VERSAL_CONSOLE_IS(dcc)) {
89 /* Initialize the dcc console for debug */
90 int32_t rc = console_dcc_register();
91 if (rc == 0) {
92 panic();
93 }
94 } else {
95 NOTICE("BL31: Did not register for any console.\n");
96 }
97
98 /* Initialize the platform config for future decision making */
99 versal_config_setup();
100 /* There are no parameters from BL2 if BL31 is a reset vector */
101 assert(arg0 == 0U);
102 assert(arg1 == 0U);
103
104 /*
105 * Do initial security configuration to allow DRAM/device access. On
106 * Base VERSAL only DRAM security is programmable (via TrustZone), but
107 * other platforms might have more programmable security devices
108 * present.
109 */
110
111 /* Populate common information for BL32 and BL33 */
112 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
113 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
114 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
115 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
116
117 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
118 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
119 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
120 if (ret_status == PM_RET_SUCCESS) {
121 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
122 atf_handoff_addr = (uintptr_t)&addr;
123 } else {
124 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read atf_handoff_addr from reg\n");
125 atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
126 }
127
128 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
129 &bl33_image_ep_info,
130 atf_handoff_addr);
131 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) {
132 bl31_set_default_config();
133 } else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) {
134 ERROR("BL31: Error too many partitions %u\n", ret);
135 } else if (ret != FSBL_HANDOFF_SUCCESS) {
136 panic();
137 } else {
138 INFO("BL31: fsbl-atf handover success %u\n", ret);
139 }
140
141 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
142 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
143 }
144
145 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
146
request_intr_type_el3(uint32_t id,interrupt_type_handler_t handler)147 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
148 {
149 static uint32_t index;
150 uint32_t i;
151
152 /* Validate 'handler' and 'id' parameters */
153 if (handler == NULL || index >= MAX_INTR_EL3) {
154 return -EINVAL;
155 }
156
157 /* Check if a handler has already been registered */
158 for (i = 0; i < index; i++) {
159 if (id == type_el3_interrupt_table[i].id) {
160 return -EALREADY;
161 }
162 }
163
164 type_el3_interrupt_table[index].id = id;
165 type_el3_interrupt_table[index].handler = handler;
166
167 index++;
168
169 return 0;
170 }
171
rdo_el3_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)172 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
173 void *handle, void *cookie)
174 {
175 uint32_t intr_id;
176 uint32_t i;
177 interrupt_type_handler_t handler = NULL;
178
179 intr_id = plat_ic_get_pending_interrupt_id();
180
181 for (i = 0; i < MAX_INTR_EL3; i++) {
182 if (intr_id == type_el3_interrupt_table[i].id) {
183 handler = type_el3_interrupt_table[i].handler;
184 }
185 }
186
187 if (handler != NULL) {
188 return handler(intr_id, flags, handle, cookie);
189 }
190
191 return 0;
192 }
bl31_platform_setup(void)193 void bl31_platform_setup(void)
194 {
195 /* Initialize the gic cpu and distributor interfaces */
196 plat_versal_gic_driver_init();
197 plat_versal_gic_init();
198 }
199
bl31_plat_runtime_setup(void)200 void bl31_plat_runtime_setup(void)
201 {
202 uint64_t flags = 0;
203 int32_t rc;
204
205 set_interrupt_rm_flag(flags, NON_SECURE);
206 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
207 rdo_el3_interrupt_handler, flags);
208 if (rc != 0) {
209 panic();
210 }
211 }
212
213 /*
214 * Perform the very early platform specific architectural setup here.
215 */
bl31_plat_arch_setup(void)216 void bl31_plat_arch_setup(void)
217 {
218 plat_arm_interconnect_init();
219 plat_arm_interconnect_enter_coherency();
220
221 const mmap_region_t bl_regions[] = {
222 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
223 MT_MEMORY | MT_RW | MT_SECURE),
224 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
225 MT_CODE | MT_SECURE),
226 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
227 MT_RO_DATA | MT_SECURE),
228 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
229 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
230 MT_DEVICE | MT_RW | MT_SECURE),
231 {0}
232 };
233
234 setup_page_tables(bl_regions, plat_versal_get_mmap());
235 enable_mmu_el3(0);
236 }
237