1 /*
2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <errno.h>
11
12 #include <bl31/bl31.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/fdt_fixup.h>
16 #include <common/fdt_wrappers.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/console.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables_v2.h>
21 #include <libfdt.h>
22 #include <plat/common/platform.h>
23 #include <plat_arm.h>
24
25 #include <plat_private.h>
26 #include <plat_startup.h>
27 #include <versal_net_def.h>
28
29 static entry_point_info_t bl32_image_ep_info;
30 static entry_point_info_t bl33_image_ep_info;
31 static console_t versal_net_runtime_console;
32
33 /*
34 * Return a pointer to the 'entry_point_info' structure of the next image for
35 * the security state specified. BL33 corresponds to the non-secure image type
36 * while BL32 corresponds to the secure image type. A NULL pointer is returned
37 * if the image does not exist.
38 */
bl31_plat_get_next_image_ep_info(uint32_t type)39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
40 {
41 assert(sec_state_is_valid(type));
42
43 if (type == NON_SECURE) {
44 return &bl33_image_ep_info;
45 }
46
47 return &bl32_image_ep_info;
48 }
49
50 /*
51 * Set the build time defaults,if we can't find any config data.
52 */
bl31_set_default_config(void)53 static inline void bl31_set_default_config(void)
54 {
55 bl32_image_ep_info.pc = BL32_BASE;
56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
57 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
58 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
59 DISABLE_ALL_EXCEPTIONS);
60 }
61
62 /*
63 * Perform any BL31 specific platform actions. Here is an opportunity to copy
64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
65 * are lost (potentially). This needs to be done before the MMU is initialized
66 * so that the memory layout can be used while creating page tables.
67 */
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
69 u_register_t arg2, u_register_t arg3)
70 {
71 uint32_t uart_clock;
72 int32_t rc;
73
74 board_detection();
75
76 switch (platform_id) {
77 case VERSAL_NET_SPP:
78 cpu_clock = 1000000;
79 uart_clock = 1000000;
80 break;
81 case VERSAL_NET_EMU:
82 cpu_clock = 3660000;
83 uart_clock = 25000000;
84 break;
85 case VERSAL_NET_QEMU:
86 /* Random values now */
87 cpu_clock = 100000000;
88 uart_clock = 25000000;
89 break;
90 case VERSAL_NET_SILICON:
91 cpu_clock = 100000000;
92 uart_clock = 100000000;
93 break;
94 default:
95 panic();
96 }
97
98 /* Initialize the console to provide early debug support */
99 rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock,
100 VERSAL_NET_UART_BAUDRATE,
101 &versal_net_runtime_console);
102 if (rc == 0) {
103 panic();
104 }
105
106 console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT |
107 CONSOLE_FLAG_RUNTIME);
108
109 NOTICE("TF-A running on Xilinx %s %d.%d\n", board_name_decode(),
110 platform_version / 10U, platform_version % 10U);
111
112 /* Initialize the platform config for future decision making */
113 versal_net_config_setup();
114 /* There are no parameters from BL2 if BL31 is a reset vector */
115 assert(arg0 == 0U);
116 assert(arg1 == 0U);
117
118 /*
119 * Do initial security configuration to allow DRAM/device access. On
120 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but
121 * other platforms might have more programmable security devices
122 * present.
123 */
124
125 /* Populate common information for BL32 and BL33 */
126 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
127 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
128 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
129 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
130
131 bl31_set_default_config();
132
133 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
134 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
135 }
136
137 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
138
request_intr_type_el3(uint32_t id,interrupt_type_handler_t handler)139 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
140 {
141 static uint32_t index;
142 uint32_t i;
143
144 /* Validate 'handler' and 'id' parameters */
145 if (handler == NULL || index >= MAX_INTR_EL3) {
146 return -EINVAL;
147 }
148
149 /* Check if a handler has already been registered */
150 for (i = 0; i < index; i++) {
151 if (id == type_el3_interrupt_table[i].id) {
152 return -EALREADY;
153 }
154 }
155
156 type_el3_interrupt_table[index].id = id;
157 type_el3_interrupt_table[index].handler = handler;
158
159 index++;
160
161 return 0;
162 }
163
rdo_el3_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)164 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
165 void *handle, void *cookie)
166 {
167 uint32_t intr_id;
168 uint32_t i;
169 interrupt_type_handler_t handler = NULL;
170
171 intr_id = plat_ic_get_pending_interrupt_id();
172
173 for (i = 0; i < MAX_INTR_EL3; i++) {
174 if (intr_id == type_el3_interrupt_table[i].id) {
175 handler = type_el3_interrupt_table[i].handler;
176 }
177 }
178
179 if (handler != NULL) {
180 handler(intr_id, flags, handle, cookie);
181 }
182
183 return 0;
184 }
185
bl31_platform_setup(void)186 void bl31_platform_setup(void)
187 {
188 /* Initialize the gic cpu and distributor interfaces */
189 plat_versal_net_gic_driver_init();
190 plat_versal_net_gic_init();
191 }
192
bl31_plat_runtime_setup(void)193 void bl31_plat_runtime_setup(void)
194 {
195 uint64_t flags = 0;
196 int32_t rc;
197
198 set_interrupt_rm_flag(flags, NON_SECURE);
199 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
200 rdo_el3_interrupt_handler, flags);
201 if (rc != 0) {
202 panic();
203 }
204 }
205
206 /*
207 * Perform the very early platform specific architectural setup here.
208 */
bl31_plat_arch_setup(void)209 void bl31_plat_arch_setup(void)
210 {
211 const mmap_region_t bl_regions[] = {
212 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
213 MT_MEMORY | MT_RW | MT_SECURE),
214 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
215 MT_CODE | MT_SECURE),
216 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
217 MT_RO_DATA | MT_SECURE),
218 {0}
219 };
220
221 setup_page_tables(bl_regions, plat_versal_net_get_mmap());
222 enable_mmu(0);
223 }
224