1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /*
8 * Zynq UltraScale+ MPSoC IPI agent registers access management
9 */
10
11 #include <errno.h>
12 #include <string.h>
13
14 #include <common/debug.h>
15 #include <common/runtime_svc.h>
16 #include <lib/bakery_lock.h>
17 #include <lib/mmio.h>
18
19 #include <ipi.h>
20 #include <plat_ipi.h>
21 #include <plat_private.h>
22
23 /* Zynqmp ipi configuration table */
24 const static struct ipi_config zynqmp_ipi_table[] = {
25 /* APU IPI */
26 {
27 .ipi_bit_mask = 0x1,
28 .ipi_reg_base = 0xFF300000U,
29 .secure_only = 0,
30 },
31 /* RPU0 IPI */
32 {
33 .ipi_bit_mask = 0x100,
34 .ipi_reg_base = 0xFF310000U,
35 .secure_only = 0,
36 },
37 /* RPU1 IPI */
38 {
39 .ipi_bit_mask = 0x200,
40 .ipi_reg_base = 0xFF320000U,
41 .secure_only = 0,
42 },
43 /* PMU0 IPI */
44 {
45 .ipi_bit_mask = 0x10000,
46 .ipi_reg_base = 0xFF330000U,
47 .secure_only = IPI_SECURE_MASK,
48 },
49 /* PMU1 IPI */
50 {
51 .ipi_bit_mask = 0x20000,
52 .ipi_reg_base = 0xFF331000U,
53 .secure_only = 0,
54 },
55 /* PMU2 IPI */
56 {
57 .ipi_bit_mask = 0x40000,
58 .ipi_reg_base = 0xFF332000U,
59 .secure_only = IPI_SECURE_MASK,
60 },
61 /* PMU3 IPI */
62 {
63 .ipi_bit_mask = 0x80000,
64 .ipi_reg_base = 0xFF333000U,
65 .secure_only = IPI_SECURE_MASK,
66 },
67 /* PL0 IPI */
68 {
69 .ipi_bit_mask = 0x1000000,
70 .ipi_reg_base = 0xFF340000U,
71 .secure_only = 0,
72 },
73 /* PL1 IPI */
74 {
75 .ipi_bit_mask = 0x2000000,
76 .ipi_reg_base = 0xFF350000U,
77 .secure_only = 0,
78 },
79 /* PL2 IPI */
80 {
81 .ipi_bit_mask = 0x4000000,
82 .ipi_reg_base = 0xFF360000U,
83 .secure_only = 0,
84 },
85 /* PL3 IPI */
86 {
87 .ipi_bit_mask = 0x8000000,
88 .ipi_reg_base = 0xFF370000U,
89 .secure_only = 0,
90 },
91 };
92
93 /**
94 * zynqmp_ipi_config_table_init() - Initialize ZynqMP IPI configuration data
95 *
96 */
zynqmp_ipi_config_table_init(void)97 void zynqmp_ipi_config_table_init(void)
98 {
99 ipi_config_table_init(zynqmp_ipi_table, ARRAY_SIZE(zynqmp_ipi_table));
100 }
101