1 /*
2  * Copyright 2021 The Hafnium Authors.
3  *
4  * Use of this source code is governed by a BSD-style
5  * license that can be found in the LICENSE file or at
6  * https://opensource.org/licenses/BSD-3-Clause.
7  */
8 
9 #include "hf/cpu.h"
10 #include "hf/dlog.h"
11 
12 #include "psci.h"
13 
14 void cpu_entry(struct cpu *c);
15 
16 /**
17  * Returns zero in context of the SPMC as it does not rely
18  * on the EL3 PSCI framework.
19  */
plat_psci_version_get(void)20 uint32_t plat_psci_version_get(void)
21 {
22 	return 0;
23 }
24 
25 /**
26  * Initialize the platform power managment module in context of
27  * running the SPMC.
28  */
plat_psci_init(void)29 void plat_psci_init(void)
30 {
31 	struct ffa_value res;
32 
33 	/*
34 	 * DEN0077A FF-A v1.1 Beta0 section 18.3.2.1.1
35 	 * Register the SPMC secondary cold boot entry point at the secure
36 	 * physical FF-A instance (to the SPMD).
37 	 */
38 	res = smc_ffa_call(
39 		(struct ffa_value){.func = FFA_SECONDARY_EP_REGISTER_64,
40 				   .arg1 = (uintreg_t)&cpu_entry});
41 
42 	if (res.func != FFA_SUCCESS_64) {
43 		panic("FFA_SECONDARY_EP_REGISTER_64 failed");
44 	}
45 }
46 
plat_psci_cpu_suspend(uint32_t power_state)47 void plat_psci_cpu_suspend(uint32_t power_state)
48 {
49 	(void)power_state;
50 }
51 
plat_psci_cpu_resume(struct cpu * c,ipaddr_t entry_point)52 void plat_psci_cpu_resume(struct cpu *c, ipaddr_t entry_point)
53 {
54 	if (cpu_on(c, entry_point, 0UL)) {
55 		/*
56 		 * This is the boot time PSCI cold reset path (svc_cpu_on_finish
57 		 * handler relayed by SPMD) on secondary cores.
58 		 */
59 		dlog_verbose("%s: cpu mpidr 0x%x ON\n", __func__, c->id);
60 	}
61 }
62