1 /*
2 * Copyright 2019 The Hafnium Authors.
3 *
4 * Use of this source code is governed by a BSD-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/BSD-3-Clause.
7 */
8
9 #include "hf/arch/vm/events.h"
10 #include "hf/arch/vm/interrupts.h"
11 #include "hf/arch/vm/interrupts_gicv3.h"
12 #include "hf/arch/vm/timer.h"
13
14 #include "hf/dlog.h"
15 #include "hf/std.h"
16
17 #include "vmapi/hf/call.h"
18
19 #include "common.h"
20 #include "test/hftest.h"
21 #include "test/vmapi/exception_handler.h"
22
23 /*
24 * Secondary VM that tries to access GICv3 system registers.
25 */
26
TEST_SERVICE(access_systemreg_ctlr)27 TEST_SERVICE(access_systemreg_ctlr)
28 {
29 exception_setup(NULL, exception_handler_skip_instruction);
30
31 /* Reading ICC_CTLR_EL1 should trap the VM. */
32 read_msr(ICC_CTLR_EL1);
33
34 /* Writing ICC_CTLR_EL1 should trap the VM. */
35 write_msr(ICC_CTLR_EL1, 0);
36
37 EXPECT_EQ(exception_handler_get_num(), 2);
38
39 /* Yield after catching the exceptions. */
40 ffa_yield();
41 }
42
TEST_SERVICE(write_systemreg_sre)43 TEST_SERVICE(write_systemreg_sre)
44 {
45 uintreg_t read;
46
47 exception_setup(NULL, exception_handler_skip_instruction);
48
49 read = read_msr(ICC_SRE_EL1);
50 if (exception_handler_get_num() != 0) {
51 /* If reads are trapped then writes should also be trapped. */
52 ASSERT_EQ(exception_handler_get_num(), 1);
53 write_msr(ICC_SRE_EL1, 0x0);
54 ASSERT_EQ(exception_handler_get_num(), 2);
55 } else {
56 ASSERT_EQ(read, 0x7);
57 /* Writing ICC_SRE_EL1 should be ignored. */
58 write_msr(ICC_SRE_EL1, 0x0);
59 ASSERT_EQ(read_msr(ICC_SRE_EL1), 0x7);
60 write_msr(ICC_SRE_EL1, 0xffffffff);
61 ASSERT_EQ(read_msr(ICC_SRE_EL1), 0x7);
62 }
63
64 ffa_yield();
65 }
66