1 /**
2 * \file
3 * \brief UTCB definitions for MIPS.
4 * \ingroup l4_utcb_api
5 */
6 #pragma once
7
8 #include <l4/sys/types.h>
9
10 /**
11 * \defgroup l4_utcb_api_mips MIPS Virtual Registers (UTCB)
12 * \ingroup l4_utcb_api
13 */
14
15 /**
16 * \brief UTCB structure for exceptions.
17 * \ingroup l4_utcb_api_mips
18 *
19 * l4_exc_regs_t matches l4_vcpu_regs_t and corresponds to
20 * fiasco/src/kern/mips32/trap_state.cpp: Trap_state_regs and
21 * entry_frame-mips32.cpp: Syscall_frame and Return_frame
22 */
23 typedef struct l4_exc_regs_t
24 {
25 l4_umword_t bad_instr_p;
26 l4_umword_t bad_instr;
27 union
28 {
29 l4_umword_t r[32]; /**< registers */
30 struct
31 {
32 l4_umword_t zero;
33 l4_umword_t at;
34 l4_umword_t v0, v1;
35 l4_umword_t a0, a1, a2, a3;
36 l4_umword_t t0, t1, t2, t3, t4, t5, t6, t7;
37 l4_umword_t s0, s1, s2, s3, s4, s5, s6, s7;
38 l4_umword_t t8, t9;
39 l4_umword_t k0, k1;
40 l4_umword_t gp;
41 l4_umword_t sp;
42 l4_umword_t s8;
43 l4_umword_t ra;
44 };
45 };
46 l4_umword_t hi, lo;
47 union
48 {
49 l4_umword_t pfa;
50 l4_umword_t bad_v_addr;
51 };
52 l4_umword_t cause;
53 l4_umword_t status;
54 union
55 {
56 l4_umword_t epc;
57 l4_umword_t ip;
58 };
59 l4_umword_t ulr;
60 } l4_exc_regs_t;
61
62 /**
63 * \brief UTCB constants for MIPS
64 * \ingroup l4_utcb_api_mips
65 * \hideinitializer
66 */
67 enum L4_utcb_consts_mips
68 {
69 L4_UTCB_EXCEPTION_REGS_SIZE = sizeof(l4_exc_regs_t) / sizeof(l4_umword_t),
70 L4_UTCB_GENERIC_DATA_SIZE = 63,
71 L4_UTCB_GENERIC_BUFFERS_SIZE = 58,
72
73 L4_UTCB_MSG_REGS_OFFSET = 0,
74 L4_UTCB_BUF_REGS_OFFSET = 64 * sizeof(l4_umword_t),
75 L4_UTCB_THREAD_REGS_OFFSET = 123 * sizeof(l4_umword_t),
76
77 L4_UTCB_INHERIT_FPU = 1UL << 24,
78
79 L4_UTCB_OFFSET = 128 * sizeof(l4_umword_t),
80 };
81
82 #include_next <l4/sys/utcb.h>
83
84 /*
85 * ==================================================================
86 * Implementations.
87 */
88
l4_utcb_direct(void)89 L4_INLINE l4_utcb_t *l4_utcb_direct(void) L4_NOTHROW
90 {
91 /* We store the UTCB pointer at offset -0x700c from the ULR value. This is
92 * compatible with MIPS TLS used by L4Re. We provide a slot in the TCB for
93 * the UTCB pointer and the TCB is stored at this offset per TLS convention.
94 * The kernel also initially sets the ULR to point 0x700c behind the UTCB
95 * pointer in the UTCB itself.
96 */
97 char const *utcb;
98 __asm__ ("rdhwr %0, $29" : "=r" (utcb));
99 return *(l4_utcb_t * const*)(utcb - 0x7000 - (3 * sizeof(void*)));
100 }
101
l4_utcb_exc_pc(l4_exc_regs_t const * u)102 L4_INLINE l4_umword_t l4_utcb_exc_pc(l4_exc_regs_t const *u) L4_NOTHROW
103 {
104 return u->epc;
105 }
106
l4_utcb_exc_pc_set(l4_exc_regs_t * u,l4_addr_t pc)107 L4_INLINE void l4_utcb_exc_pc_set(l4_exc_regs_t *u, l4_addr_t pc) L4_NOTHROW
108 {
109 u->epc = pc;
110 }
111
l4_utcb_exc_typeval(l4_exc_regs_t const * u)112 L4_INLINE l4_umword_t l4_utcb_exc_typeval(l4_exc_regs_t const *u) L4_NOTHROW
113 {
114 return u->cause & 0x1ff;
115 }
116
l4_utcb_exc_is_pf(l4_exc_regs_t const * u)117 L4_INLINE int l4_utcb_exc_is_pf(l4_exc_regs_t const *u) L4_NOTHROW
118 {
119 unsigned c = (u->cause >> 2) & 0x1f;
120 return ((1 <= c) && (c <= 7)) || ((19 <= c) && (c <= 20));
121 }
122
l4_utcb_exc_pfa(l4_exc_regs_t const * u)123 L4_INLINE l4_addr_t l4_utcb_exc_pfa(l4_exc_regs_t const *u) L4_NOTHROW
124 {
125 return (u->bad_v_addr & ~7) | ((u->cause >> 1) & 2);
126 }
127
l4_utcb_exc_is_ex_regs_exception(l4_exc_regs_t const * u)128 L4_INLINE int l4_utcb_exc_is_ex_regs_exception(l4_exc_regs_t const *u) L4_NOTHROW
129 {
130 return l4_utcb_exc_typeval(u) == 0x101;
131 }
132