1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas 9-series I2C PCIe clock generators
8
9description: |
10  The Renesas 9-series are I2C PCIe clock generators providing
11  from 1 to 20 output clocks.
12
13  When referencing the provided clock in the DT using phandle
14  and clock specifier, the following mapping applies:
15
16  - 9FGV0241:
17    0 -- DIF0
18    1 -- DIF1
19
20maintainers:
21  - Marek Vasut <marex@denx.de>
22
23properties:
24  compatible:
25    enum:
26      - renesas,9fgv0241
27
28  reg:
29    description: I2C device address
30    enum: [ 0x68, 0x6a ]
31
32  '#clock-cells':
33    const: 1
34
35  clocks:
36    items:
37      - description: XTal input clock
38
39  renesas,out-amplitude-microvolt:
40    enum: [ 600000, 700000, 800000, 900000 ]
41    description: Output clock signal amplitude
42
43  renesas,out-spread-spectrum:
44    $ref: /schemas/types.yaml#/definitions/uint32
45    enum: [ 100000, 99750, 99500 ]
46    description: Output clock down spread in pcm (1/1000 of percent)
47
48patternProperties:
49  "^DIF[0-19]$":
50    type: object
51    description:
52      Description of one of the outputs (DIF0..DIF19).
53
54    properties:
55      renesas,slew-rate:
56        $ref: /schemas/types.yaml#/definitions/uint32
57        enum: [ 2000000, 3000000 ]
58        description: Output clock slew rate select in V/ns
59
60    additionalProperties: false
61
62required:
63  - compatible
64  - reg
65  - clocks
66  - '#clock-cells'
67
68additionalProperties: false
69
70examples:
71  - |
72    /* 25MHz reference crystal */
73    ref25: ref25m {
74        compatible = "fixed-clock";
75        #clock-cells = <0>;
76        clock-frequency = <25000000>;
77    };
78
79    i2c@0 {
80        reg = <0x0 0x100>;
81        #address-cells = <1>;
82        #size-cells = <0>;
83
84        rs9: clock-generator@6a {
85            compatible = "renesas,9fgv0241";
86            reg = <0x6a>;
87            #clock-cells = <1>;
88
89            clocks = <&ref25m>;
90
91            DIF0 {
92                renesas,slew-rate = <3000000>;
93            };
94        };
95    };
96
97...
98