1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - const: qcom,cpufreq-hw
24
25      - description: v2 of CPUFREQ HW (EPSS)
26        items:
27          - enum:
28              - qcom,qdu1000-cpufreq-epss
29              - qcom,sc7280-cpufreq-epss
30              - qcom,sc8280xp-cpufreq-epss
31              - qcom,sm6375-cpufreq-epss
32              - qcom,sm8250-cpufreq-epss
33              - qcom,sm8350-cpufreq-epss
34              - qcom,sm8450-cpufreq-epss
35              - qcom,sm8550-cpufreq-epss
36          - const: qcom,cpufreq-epss
37
38  reg:
39    minItems: 2
40    items:
41      - description: Frequency domain 0 register region
42      - description: Frequency domain 1 register region
43      - description: Frequency domain 2 register region
44
45  reg-names:
46    minItems: 2
47    items:
48      - const: freq-domain0
49      - const: freq-domain1
50      - const: freq-domain2
51
52  clocks:
53    items:
54      - description: XO Clock
55      - description: GPLL0 Clock
56
57  clock-names:
58    items:
59      - const: xo
60      - const: alternate
61
62  interrupts:
63    minItems: 1
64    maxItems: 3
65
66  interrupt-names:
67    minItems: 1
68    items:
69      - const: dcvsh-irq-0
70      - const: dcvsh-irq-1
71      - const: dcvsh-irq-2
72
73  '#freq-domain-cells':
74    const: 1
75
76  '#clock-cells':
77    const: 1
78
79required:
80  - compatible
81  - reg
82  - clocks
83  - clock-names
84  - '#freq-domain-cells'
85
86additionalProperties: false
87
88examples:
89  - |
90    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
91    #include <dt-bindings/clock/qcom,rpmh.h>
92
93    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
94    // switch DCVS state together.
95    cpus {
96      #address-cells = <2>;
97      #size-cells = <0>;
98
99      CPU0: cpu@0 {
100        device_type = "cpu";
101        compatible = "qcom,kryo385";
102        reg = <0x0 0x0>;
103        enable-method = "psci";
104        next-level-cache = <&L2_0>;
105        qcom,freq-domain = <&cpufreq_hw 0>;
106        clocks = <&cpufreq_hw 0>;
107        L2_0: l2-cache {
108          compatible = "cache";
109          cache-unified;
110          cache-level = <2>;
111          next-level-cache = <&L3_0>;
112          L3_0: l3-cache {
113            compatible = "cache";
114            cache-unified;
115            cache-level = <3>;
116          };
117        };
118      };
119
120      CPU1: cpu@100 {
121        device_type = "cpu";
122        compatible = "qcom,kryo385";
123        reg = <0x0 0x100>;
124        enable-method = "psci";
125        next-level-cache = <&L2_100>;
126        qcom,freq-domain = <&cpufreq_hw 0>;
127        clocks = <&cpufreq_hw 0>;
128        L2_100: l2-cache {
129          compatible = "cache";
130          cache-unified;
131          cache-level = <2>;
132          next-level-cache = <&L3_0>;
133        };
134      };
135
136      CPU2: cpu@200 {
137        device_type = "cpu";
138        compatible = "qcom,kryo385";
139        reg = <0x0 0x200>;
140        enable-method = "psci";
141        next-level-cache = <&L2_200>;
142        qcom,freq-domain = <&cpufreq_hw 0>;
143        clocks = <&cpufreq_hw 0>;
144        L2_200: l2-cache {
145          compatible = "cache";
146          cache-unified;
147          cache-level = <2>;
148          next-level-cache = <&L3_0>;
149        };
150      };
151
152      CPU3: cpu@300 {
153        device_type = "cpu";
154        compatible = "qcom,kryo385";
155        reg = <0x0 0x300>;
156        enable-method = "psci";
157        next-level-cache = <&L2_300>;
158        qcom,freq-domain = <&cpufreq_hw 0>;
159        clocks = <&cpufreq_hw 0>;
160        L2_300: l2-cache {
161          compatible = "cache";
162          cache-unified;
163          cache-level = <2>;
164          next-level-cache = <&L3_0>;
165        };
166      };
167
168      CPU4: cpu@400 {
169        device_type = "cpu";
170        compatible = "qcom,kryo385";
171        reg = <0x0 0x400>;
172        enable-method = "psci";
173        next-level-cache = <&L2_400>;
174        qcom,freq-domain = <&cpufreq_hw 1>;
175        clocks = <&cpufreq_hw 1>;
176        L2_400: l2-cache {
177          compatible = "cache";
178          cache-unified;
179          cache-level = <2>;
180          next-level-cache = <&L3_0>;
181        };
182      };
183
184      CPU5: cpu@500 {
185        device_type = "cpu";
186        compatible = "qcom,kryo385";
187        reg = <0x0 0x500>;
188        enable-method = "psci";
189        next-level-cache = <&L2_500>;
190        qcom,freq-domain = <&cpufreq_hw 1>;
191        clocks = <&cpufreq_hw 1>;
192        L2_500: l2-cache {
193          compatible = "cache";
194          cache-unified;
195          cache-level = <2>;
196          next-level-cache = <&L3_0>;
197        };
198      };
199
200      CPU6: cpu@600 {
201        device_type = "cpu";
202        compatible = "qcom,kryo385";
203        reg = <0x0 0x600>;
204        enable-method = "psci";
205        next-level-cache = <&L2_600>;
206        qcom,freq-domain = <&cpufreq_hw 1>;
207        clocks = <&cpufreq_hw 1>;
208        L2_600: l2-cache {
209          compatible = "cache";
210          cache-unified;
211          cache-level = <2>;
212          next-level-cache = <&L3_0>;
213        };
214      };
215
216      CPU7: cpu@700 {
217        device_type = "cpu";
218        compatible = "qcom,kryo385";
219        reg = <0x0 0x700>;
220        enable-method = "psci";
221        next-level-cache = <&L2_700>;
222        qcom,freq-domain = <&cpufreq_hw 1>;
223        clocks = <&cpufreq_hw 1>;
224        L2_700: l2-cache {
225          compatible = "cache";
226          cache-unified;
227          cache-level = <2>;
228          next-level-cache = <&L3_0>;
229        };
230      };
231    };
232
233    soc {
234      #address-cells = <1>;
235      #size-cells = <1>;
236
237      cpufreq@17d43000 {
238        compatible = "qcom,cpufreq-hw";
239        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
240        reg-names = "freq-domain0", "freq-domain1";
241
242        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
243        clock-names = "xo", "alternate";
244
245        #freq-domain-cells = <1>;
246        #clock-cells = <1>;
247      };
248    };
249...
250