1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6115 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for SM6115 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm6115-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AXI clock
27      - description: Display core clock
28
29  iommus:
30    maxItems: 2
31
32patternProperties:
33  "^display-controller@[0-9a-f]+$":
34    type: object
35    properties:
36      compatible:
37        const: qcom,sm6115-dpu
38
39  "^dsi@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        const: qcom,dsi-ctrl-6g-qcm2290
44
45  "^phy@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        const: qcom,dsi-phy-14nm-2290
50
51required:
52  - compatible
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
59    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
60    #include <dt-bindings/clock/qcom,rpmcc.h>
61    #include <dt-bindings/interrupt-controller/arm-gic.h>
62    #include <dt-bindings/power/qcom-rpmpd.h>
63
64    display-subsystem@5e00000 {
65        #address-cells = <1>;
66        #size-cells = <1>;
67        compatible = "qcom,sm6115-mdss";
68        reg = <0x05e00000 0x1000>;
69        reg-names = "mdss";
70        power-domains = <&dispcc MDSS_GDSC>;
71        clocks = <&gcc GCC_DISP_AHB_CLK>,
72                 <&gcc GCC_DISP_HF_AXI_CLK>,
73                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
74
75        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
76        interrupt-controller;
77        #interrupt-cells = <1>;
78
79        iommus = <&apps_smmu 0x420 0x2>,
80                 <&apps_smmu 0x421 0x0>;
81        ranges;
82
83        display-controller@5e01000 {
84            compatible = "qcom,sm6115-dpu";
85            reg = <0x05e01000 0x8f000>,
86                  <0x05eb0000 0x2008>;
87            reg-names = "mdp", "vbif";
88
89            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
90                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
91                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
92                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
93                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
94                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
95            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
96
97            operating-points-v2 = <&mdp_opp_table>;
98            power-domains = <&rpmpd SM6115_VDDCX>;
99
100            interrupt-parent = <&mdss>;
101            interrupts = <0>;
102
103            ports {
104                #address-cells = <1>;
105                #size-cells = <0>;
106
107                port@0 {
108                    reg = <0>;
109                    dpu_intf1_out: endpoint {
110                        remote-endpoint = <&dsi0_in>;
111                    };
112                };
113            };
114        };
115
116        dsi@5e94000 {
117            compatible = "qcom,dsi-ctrl-6g-qcm2290";
118            reg = <0x05e94000 0x400>;
119            reg-names = "dsi_ctrl";
120
121            interrupt-parent = <&mdss>;
122            interrupts = <4>;
123
124            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
125                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
126                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
127                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
128                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
129                     <&gcc GCC_DISP_HF_AXI_CLK>;
130            clock-names = "byte",
131                          "byte_intf",
132                          "pixel",
133                          "core",
134                          "iface",
135                          "bus";
136            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
137            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
138
139            operating-points-v2 = <&dsi_opp_table>;
140            power-domains = <&rpmpd SM6115_VDDCX>;
141            phys = <&dsi0_phy>;
142
143            #address-cells = <1>;
144            #size-cells = <0>;
145
146            ports {
147                #address-cells = <1>;
148                #size-cells = <0>;
149
150                port@0 {
151                    reg = <0>;
152                    dsi0_in: endpoint {
153                        remote-endpoint = <&dpu_intf1_out>;
154                    };
155                };
156
157                port@1 {
158                    reg = <1>;
159                    dsi0_out: endpoint {
160                    };
161                };
162            };
163        };
164
165        dsi0_phy: phy@5e94400 {
166            compatible = "qcom,dsi-phy-14nm-2290";
167            reg = <0x05e94400 0x100>,
168                  <0x05e94500 0x300>,
169                  <0x05e94800 0x188>;
170            reg-names = "dsi_phy",
171                        "dsi_phy_lane",
172                        "dsi_pll";
173
174            #clock-cells = <1>;
175            #phy-cells = <0>;
176
177            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
178            clock-names = "iface", "ref";
179        };
180    };
181...
182