1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arasan SDHCI Controller
8
9maintainers:
10  - Adrian Hunter <adrian.hunter@intel.com>
11
12allOf:
13  - $ref: mmc-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: arasan,sdhci-5.1
19    then:
20      required:
21        - phys
22        - phy-names
23  - if:
24      properties:
25        compatible:
26          contains:
27            enum:
28              - xlnx,zynqmp-8.9a
29              - xlnx,versal-8.9a
30    then:
31      properties:
32        clock-output-names:
33          oneOf:
34            - items:
35                - const: clk_out_sd0
36                - const: clk_in_sd0
37            - items:
38                - const: clk_out_sd1
39                - const: clk_in_sd1
40
41properties:
42  compatible:
43    oneOf:
44      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
45      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
46      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
47      - items:
48          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
49          - const: arasan,sdhci-5.1
50        description:
51          For this device it is strongly suggested to include
52          arasan,soc-ctl-syscon.
53      - items:
54          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
55          - const: arasan,sdhci-8.9a
56        description:
57          For this device it is strongly suggested to include
58          clock-output-names and '#clock-cells'.
59      - items:
60          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
61          - const: arasan,sdhci-8.9a
62        description:
63          For this device it is strongly suggested to include
64          clock-output-names and '#clock-cells'.
65      - items:
66          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
67          - const: arasan,sdhci-5.1
68        description:
69          For this device it is strongly suggested to include
70          arasan,soc-ctl-syscon.
71      - items:
72          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
73          - const: arasan,sdhci-5.1
74        description:
75          For this device it is strongly suggested to include
76          arasan,soc-ctl-syscon.
77      - items:
78          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79          - const: arasan,sdhci-5.1
80        description:
81          For this device it is strongly suggested to include
82          arasan,soc-ctl-syscon.
83      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
84        description:
85          For this device it is strongly suggested to include
86          arasan,soc-ctl-syscon.
87      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
88        description:
89          For this device it is strongly suggested to include
90          arasan,soc-ctl-syscon.
91      - items:
92          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
93          - const: arasan,sdhci-5.1
94        description:
95          For this device it is strongly suggested to include
96          clock-output-names and '#clock-cells'.
97
98  reg:
99    maxItems: 1
100
101  clocks:
102    minItems: 2
103    maxItems: 3
104
105  clock-names:
106    minItems: 2
107    items:
108      - const: clk_xin
109      - const: clk_ahb
110      - const: gate
111
112  interrupts:
113    maxItems: 1
114
115  phys:
116    maxItems: 1
117
118  phy-names:
119    const: phy_arasan
120
121  resets:
122    maxItems: 1
123
124  arasan,soc-ctl-syscon:
125    $ref: /schemas/types.yaml#/definitions/phandle
126    description:
127      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
128      core corecfg registers. Offsets of registers in this syscon are
129      determined based on the main compatible string for the device.
130
131  clock-output-names:
132    minItems: 1
133    maxItems: 2
134    description:
135      Name of the card clock which will be exposed by this device.
136
137  '#clock-cells':
138    enum: [0, 1]
139    description:
140      With this property in place we will export one or two clocks
141      representing the Card Clock. These clocks are expected to be
142      consumed by our PHY.
143
144  xlnx,fails-without-test-cd:
145    $ref: /schemas/types.yaml#/definitions/flag
146    description:
147      When present, the controller doesn't work when the CD line is not
148      connected properly, and the line is not connected properly.
149      Test mode can be used to force the controller to function.
150
151  xlnx,int-clock-stable-broken:
152    $ref: /schemas/types.yaml#/definitions/flag
153    description:
154      When present, the controller always reports that the internal clock
155      is stable even when it is not.
156
157  xlnx,mio-bank:
158    $ref: /schemas/types.yaml#/definitions/uint32
159    enum: [0, 1, 2]
160    default: 0
161    description:
162      The MIO bank number in which the command and data lines are configured.
163
164dependencies:
165  '#clock-cells': [ clock-output-names ]
166
167required:
168  - compatible
169  - reg
170  - interrupts
171  - clocks
172  - clock-names
173
174unevaluatedProperties: false
175
176examples:
177  - |
178    mmc@e0100000 {
179          compatible = "arasan,sdhci-8.9a";
180          reg = <0xe0100000 0x1000>;
181          clock-names = "clk_xin", "clk_ahb";
182          clocks = <&clkc 21>, <&clkc 32>;
183          interrupt-parent = <&gic>;
184          interrupts = <0 24 4>;
185    };
186
187  - |
188    mmc@e2800000 {
189          compatible = "arasan,sdhci-5.1";
190          reg = <0xe2800000 0x1000>;
191          clock-names = "clk_xin", "clk_ahb";
192          clocks = <&cru 8>, <&cru 18>;
193          interrupt-parent = <&gic>;
194          interrupts = <0 24 4>;
195          phys = <&emmc_phy>;
196          phy-names = "phy_arasan";
197    };
198
199  - |
200    #include <dt-bindings/clock/rk3399-cru.h>
201    #include <dt-bindings/interrupt-controller/arm-gic.h>
202    #include <dt-bindings/interrupt-controller/irq.h>
203    mmc@fe330000 {
204          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
205          reg = <0xfe330000 0x10000>;
206          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
207          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
208          clock-names = "clk_xin", "clk_ahb";
209          arasan,soc-ctl-syscon = <&grf>;
210          assigned-clocks = <&cru SCLK_EMMC>;
211          assigned-clock-rates = <200000000>;
212          clock-output-names = "emmc_cardclock";
213          phys = <&emmc_phy>;
214          phy-names = "phy_arasan";
215          #clock-cells = <0>;
216    };
217
218  - |
219    mmc@ff160000 {
220          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
221          interrupt-parent = <&gic>;
222          interrupts = <0 48 4>;
223          reg = <0xff160000 0x1000>;
224          clocks = <&clk200>, <&clk200>;
225          clock-names = "clk_xin", "clk_ahb";
226          clock-output-names = "clk_out_sd0", "clk_in_sd0";
227          #clock-cells = <1>;
228          clk-phase-sd-hs = <63>, <72>;
229    };
230
231  - |
232    mmc@f1040000 {
233          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
234          interrupt-parent = <&gic>;
235          interrupts = <0 126 4>;
236          reg = <0xf1040000 0x10000>;
237          clocks = <&clk200>, <&clk200>;
238          clock-names = "clk_xin", "clk_ahb";
239          clock-output-names = "clk_out_sd0", "clk_in_sd0";
240          #clock-cells = <1>;
241          clk-phase-sd-hs = <132>, <60>;
242    };
243
244  - |
245    #define LGM_CLK_EMMC5
246    #define LGM_CLK_NGI
247    #define LGM_GCLK_EMMC
248    mmc@ec700000 {
249          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
250          reg = <0xec700000 0x300>;
251          interrupt-parent = <&ioapic1>;
252          interrupts = <44 1>;
253          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
254                   <&cgu0 LGM_GCLK_EMMC>;
255          clock-names = "clk_xin", "clk_ahb", "gate";
256          clock-output-names = "emmc_cardclock";
257          #clock-cells = <0>;
258          phys = <&emmc_phy>;
259          phy-names = "phy_arasan";
260          arasan,soc-ctl-syscon = <&sysconf>;
261    };
262
263  - |
264    #define LGM_CLK_SDIO
265    #define LGM_GCLK_SDXC
266    mmc@ec600000 {
267          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
268          reg = <0xec600000 0x300>;
269          interrupt-parent = <&ioapic1>;
270          interrupts = <43 1>;
271          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
272                   <&cgu0 LGM_GCLK_SDXC>;
273          clock-names = "clk_xin", "clk_ahb", "gate";
274          clock-output-names = "sdxc_cardclock";
275          #clock-cells = <0>;
276          phys = <&sdxc_phy>;
277          phy-names = "phy_arasan";
278          arasan,soc-ctl-syscon = <&sysconf>;
279    };
280
281  - |
282    #define KEEM_BAY_PSS_AUX_EMMC
283    #define KEEM_BAY_PSS_EMMC
284    mmc@33000000 {
285          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
286          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
287          reg = <0x33000000 0x300>;
288          clock-names = "clk_xin", "clk_ahb";
289          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
290                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
291          phys = <&emmc_phy>;
292          phy-names = "phy_arasan";
293          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
294          assigned-clock-rates = <200000000>;
295          clock-output-names = "emmc_cardclock";
296          #clock-cells = <0>;
297          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
298    };
299
300  - |
301    #define KEEM_BAY_PSS_AUX_SD0
302    #define KEEM_BAY_PSS_SD0
303    mmc@31000000 {
304          compatible = "intel,keembay-sdhci-5.1-sd";
305          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
306          reg = <0x31000000 0x300>;
307          clock-names = "clk_xin", "clk_ahb";
308          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
309                   <&scmi_clk KEEM_BAY_PSS_SD0>;
310          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
311    };
312
313  - |
314    #define EMMC_XIN_CLK
315    #define EMMC_AXI_CLK
316    #define TBH_PSS_EMMC_RST_N
317    mmc@80420000 {
318          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
319          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
320          reg = <0x80420000 0x400>;
321          clocks = <&scmi_clk EMMC_XIN_CLK>,
322                   <&scmi_clk EMMC_AXI_CLK>;
323          clock-names = "clk_xin", "clk_ahb";
324          phys = <&emmc_phy>;
325          phy-names = "phy_arasan";
326          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
327          clock-output-names = "emmc_cardclock";
328          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
329          #clock-cells = <0x0>;
330    };
331