1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP FMan MAC
8
9maintainers:
10  - Madalin Bucur <madalin.bucur@nxp.com>
11
12description: |
13  Each FMan has several MACs, each implementing an Ethernet interface. Earlier
14  versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
15  10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
16  (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
17  Ethernet Media Access Controller (mEMAC) to handle all speeds.
18
19properties:
20  compatible:
21    enum:
22      - fsl,fman-dtsec
23      - fsl,fman-xgec
24      - fsl,fman-memac
25
26  cell-index:
27    maximum: 64
28    description: |
29      FManV2:
30      register[bit]           MAC             cell-index
31      ============================================================
32      FM_EPI[16]              XGEC            8
33      FM_EPI[16+n]            dTSECn          n-1
34      FM_NPI[11+n]            dTSECn          n-1
35              n = 1,..,5
36
37      FManV3:
38      register[bit]           MAC             cell-index
39      ============================================================
40      FM_EPI[16+n]            mEMACn          n-1
41      FM_EPI[25]              mEMAC10         9
42
43      FM_NPI[11+n]            mEMACn          n-1
44      FM_NPI[10]              mEMAC10         9
45      FM_NPI[11]              mEMAC9          8
46              n = 1,..8
47
48      FM_EPI and FM_NPI are located in the FMan memory map.
49
50      2. SoC registers:
51
52      - P2041, P3041, P4080 P5020, P5040:
53      register[bit]           FMan            MAC             cell
54                              Unit                            index
55      ============================================================
56      DCFG_DEVDISR2[7]        1               XGEC            8
57      DCFG_DEVDISR2[7+n]      1               dTSECn          n-1
58      DCFG_DEVDISR2[15]       2               XGEC            8
59      DCFG_DEVDISR2[15+n]     2               dTSECn          n-1
60              n = 1,..5
61
62      - T1040, T2080, T4240, B4860:
63      register[bit]                   FMan    MAC             cell
64                                      Unit                    index
65      ============================================================
66      DCFG_CCSR_DEVDISR2[n-1]         1       mEMACn          n-1
67      DCFG_CCSR_DEVDISR2[11+n]        2       mEMACn          n-1
68              n = 1,..6,9,10
69
70      EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
71      the specific SoC "Device Configuration/Pin Control" Memory
72      Map.
73
74  reg:
75    maxItems: 1
76
77  fsl,fman-ports:
78    $ref: /schemas/types.yaml#/definitions/phandle-array
79    maxItems: 2
80    description: |
81      An array of two references: the first is the FMan RX port and the second
82      is the TX port used by this MAC.
83
84  ptp-timer:
85    $ref: /schemas/types.yaml#/definitions/phandle
86    description: A reference to the IEEE1588 timer
87
88  phys:
89    description: A reference to the SerDes lane(s)
90    maxItems: 1
91
92  phy-names:
93    items:
94      - const: serdes
95
96  pcsphy-handle:
97    $ref: /schemas/types.yaml#/definitions/phandle-array
98    minItems: 1
99    maxItems: 3
100    deprecated: true
101    description: See pcs-handle.
102
103  pcs-handle:
104    minItems: 1
105    maxItems: 3
106    description: |
107      A reference to the various PCSs (typically found on the SerDes). If
108      pcs-handle-names is absent, and phy-connection-type is "xgmii", then the first
109      reference will be assumed to be for "xfi". Otherwise, if pcs-handle-names is
110      absent, then the first reference will be assumed to be for "sgmii".
111
112  pcs-handle-names:
113    minItems: 1
114    maxItems: 3
115    items:
116      enum:
117        - sgmii
118        - qsgmii
119        - xfi
120    description: The type of each PCS in pcsphy-handle.
121
122  tbi-handle:
123    $ref: /schemas/types.yaml#/definitions/phandle
124    description: A reference to the (TBI-based) PCS
125
126required:
127  - compatible
128  - cell-index
129  - reg
130  - fsl,fman-ports
131  - ptp-timer
132
133dependencies:
134  pcs-handle-names:
135    - pcs-handle
136
137allOf:
138  - $ref: ethernet-controller.yaml#
139  - if:
140      properties:
141        compatible:
142          contains:
143            const: fsl,fman-dtsec
144    then:
145      required:
146        - tbi-handle
147
148unevaluatedProperties: false
149
150examples:
151  - |
152    ethernet@e0000 {
153            compatible = "fsl,fman-dtsec";
154            cell-index = <0>;
155            reg = <0xe0000 0x1000>;
156            fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
157            ptp-timer = <&ptp_timer>;
158            tbi-handle = <&tbi0>;
159    };
160  - |
161    ethernet@e8000 {
162            cell-index = <4>;
163            compatible = "fsl,fman-memac";
164            reg = <0xe8000 0x1000>;
165            fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
166            ptp-timer = <&ptp_timer0>;
167            pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
168            pcs-handle-names = "sgmii", "qsgmii";
169            phys = <&serdes1 1>;
170            phy-names = "serdes";
171    };
172...
173