1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare PCIe endpoint interface
8
9maintainers:
10  - Jingoo Han <jingoohan1@gmail.com>
11  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
12
13description: |
14  Synopsys DesignWare PCIe host controller endpoint
15
16# Please create a separate DT-schema for your DWC PCIe Endpoint controller
17# and make sure it's assigned with the vendor-specific compatible string.
18select:
19  properties:
20    compatible:
21      const: snps,dw-pcie-ep
22  required:
23    - compatible
24
25allOf:
26  - $ref: /schemas/pci/pci-ep.yaml#
27  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
28
29properties:
30  reg:
31    description:
32      DBI, DBI2 reg-spaces and outbound memory window are required for the
33      normal controller functioning. iATU memory IO region is also required
34      if the space is unrolled (IP-core version >= 4.80a).
35    minItems: 2
36    maxItems: 5
37
38  reg-names:
39    minItems: 2
40    maxItems: 5
41    items:
42      oneOf:
43        - description:
44            Basic DWC PCIe controller configuration-space accessible over
45            the DBI interface. This memory space is either activated with
46            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
47            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
48            via the PL viewports on the DWC PCIe controllers older than
49            v4.80a.
50          const: dbi
51        - description:
52            Shadow DWC PCIe config-space registers. This space is selected
53            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
54            the PCI-SIG PCIe CFG-space with the shadow registers for some
55            PCI Header space, PCI Standard and Extended Structures. It's
56            mainly relevant for the end-point controller configuration,
57            but still there are some shadow registers available for the
58            Root Port mode too.
59          const: dbi2
60        - description:
61            External Local Bus registers. It's an application-dependent
62            registers normally defined by the platform engineers. The space
63            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
64            be accessed over some platform-specific means (for instance
65            as a part of a system controller).
66          enum: [ elbi, app ]
67        - description:
68            iATU/eDMA registers common for all device functions. It's an
69            unrolled memory space with the internal Address Translation
70            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
71            and CS2 = 1. For IP-core releases prior v4.80a, these registers
72            have been programmed via an indirect addressing scheme using a
73            set of viewport CSRs mapped into the PL space. Note iATU is
74            normally mapped to the 0x0 address of this region, while eDMA
75            is available at 0x80000 base address.
76          const: atu
77        - description:
78            Platform-specific eDMA registers. Some platforms may have eDMA
79            CSRs mapped in a non-standard base address. The registers offset
80            can be changed or the MS/LS-bits of the address can be attached
81            in an additional RTL block before the MEM-IO transactions reach
82            the DW PCIe slave interface.
83          const: dma
84        - description:
85            PHY/PCS configuration registers. Some platforms can have the
86            PCS and PHY CSRs accessible over a dedicated memory mapped
87            region, but mainly these registers are indirectly accessible
88            either by means of the embedded PHY viewport schema or by some
89            platform-specific method.
90          const: phy
91        - description:
92            Outbound iATU-capable memory-region which will be used to
93            generate various application-specific traffic on the PCIe bus
94            hierarchy. It's usage scenario depends on the endpoint
95            functionality, for instance it can be used to create MSI(X)
96            messages.
97          const: addr_space
98        - description:
99            Vendor-specific CSR names. Consider using the generic names above
100            for new bindings.
101          oneOf:
102            - description: See native 'elbi/app' CSR region for details.
103              enum: [ link, appl ]
104            - description: See native 'atu' CSR region for details.
105              enum: [ atu_dma ]
106    allOf:
107      - contains:
108          const: dbi
109      - contains:
110          const: addr_space
111
112  interrupts:
113    description:
114      There is no mandatory IRQ signals for the normal controller functioning,
115      but in addition to the native set the platforms may have a link- or
116      PM-related IRQs specified.
117    minItems: 1
118    maxItems: 20
119
120  interrupt-names:
121    minItems: 1
122    maxItems: 20
123    items:
124      oneOf:
125        - description:
126            Controller request to read or write virtual product data
127            from/to the VPD capability registers.
128          const: vpd
129        - description:
130            Link Equalization Request flag is set in the Link Status 2
131            register (applicable if the corresponding IRQ is enabled in
132            the Link Control 3 register).
133          const: l_eq
134        - description:
135            Indicates that the eDMA Tx/Rx transfer is complete or that an
136            error has occurred on the corresponding channel. eDMA can have
137            eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138            to 16 IRQ signals all together. Write eDMA channels shall go
139            first in the ordered row as per default edma_int[*] bus setup.
140          pattern: '^dma([0-9]|1[0-5])?$'
141        - description:
142            PCIe protocol correctable error or a Data Path protection
143            correctable error is detected by the automotive/safety
144            feature.
145          const: sft_ce
146        - description:
147            Indicates that the internal safety mechanism has detected an
148            uncorrectable error.
149          const: sft_ue
150        - description:
151            Application-specific IRQ raised depending on the vendor-specific
152            events basis.
153          const: app
154        - description:
155            Vendor-specific IRQ names. Consider using the generic names above
156            for new bindings.
157          oneOf:
158            - description: See native "app" IRQ for details
159              enum: [ intr ]
160
161  max-functions:
162    maximum: 32
163
164required:
165  - compatible
166  - reg
167  - reg-names
168
169additionalProperties: true
170
171examples:
172  - |
173    pcie-ep@dfd00000 {
174      compatible = "snps,dw-pcie-ep";
175      reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
176            <0xdfc01000 0x0001000>, /* IP registers 2 */
177            <0xd0000000 0x2000000>; /* Configuration space */
178      reg-names = "dbi", "dbi2", "addr_space";
179
180      interrupts = <23>, <24>;
181      interrupt-names = "dma0", "dma1";
182
183      clocks = <&sys_clk 12>, <&sys_clk 24>;
184      clock-names = "dbi", "ref";
185
186      resets = <&sys_rst 12>, <&sys_rst 24>;
187      reset-names = "dbi", "phy";
188
189      phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
190      phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
191
192      max-link-speed = <3>;
193      max-functions = /bits/ 8 <4>;
194    };
195