1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QMP USB3 DP PHY controller (SC7180)
9
10description:
11  The QMP PHY controller supports physical layer functionality for a number of
12  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
13
14  Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
15  qcom,sc8280xp-qmp-usb43dp-phy.yaml.
16
17maintainers:
18  - Wesley Cheng <quic_wcheng@quicinc.com>
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - qcom,sc7180-qmp-usb3-dp-phy
25          - qcom,sc8180x-qmp-usb3-dp-phy
26          - qcom,sdm845-qmp-usb3-dp-phy
27          - qcom,sm8250-qmp-usb3-dp-phy
28      - items:
29          - enum:
30              - qcom,sc7280-qmp-usb3-dp-phy
31          - const: qcom,sm8250-qmp-usb3-dp-phy
32
33  reg:
34    items:
35      - description: Address and length of PHY's USB serdes block.
36      - description: Address and length of the DP_COM control block.
37      - description: Address and length of PHY's DP serdes block.
38
39  reg-names:
40    items:
41      - const: usb
42      - const: dp_com
43      - const: dp
44
45  "#address-cells":
46    enum: [ 1, 2 ]
47
48  "#size-cells":
49    enum: [ 1, 2 ]
50
51  ranges: true
52
53  clocks:
54    minItems: 3
55    maxItems: 4
56
57  clock-names:
58    minItems: 3
59    maxItems: 4
60
61  power-domains:
62    maxItems: 1
63
64  resets:
65    items:
66      - description: reset of phy block.
67      - description: phy common block reset.
68
69  reset-names:
70    items:
71      - const: phy
72      - const: common
73
74  vdda-phy-supply:
75    description:
76      Phandle to a regulator supply to PHY core block.
77
78  vdda-pll-supply:
79    description:
80      Phandle to 1.8V regulator supply to PHY refclk pll block.
81
82  vddp-ref-clk-supply:
83    description:
84      Phandle to a regulator supply to any specific refclk pll block.
85
86#Required nodes:
87patternProperties:
88  "^usb3-phy@[0-9a-f]+$":
89    type: object
90    additionalProperties: false
91    description:
92      The USB3 PHY.
93
94    properties:
95      reg:
96        items:
97          - description: Address and length of TX.
98          - description: Address and length of RX.
99          - description: Address and length of PCS.
100          - description: Address and length of TX2.
101          - description: Address and length of RX2.
102          - description: Address and length of pcs_misc.
103
104      clocks:
105        items:
106          - description: pipe clock
107
108      clock-names:
109        deprecated: true
110        items:
111          - const: pipe0
112
113      clock-output-names:
114        items:
115          - const: usb3_phy_pipe_clk_src
116
117      '#clock-cells':
118        const: 0
119
120      '#phy-cells':
121        const: 0
122
123    required:
124      - reg
125      - clocks
126      - '#clock-cells'
127      - '#phy-cells'
128
129  "^dp-phy@[0-9a-f]+$":
130    type: object
131    additionalProperties: false
132    description:
133      The DP PHY.
134
135    properties:
136      reg:
137        items:
138          - description: Address and length of TX.
139          - description: Address and length of RX.
140          - description: Address and length of PCS.
141          - description: Address and length of TX2.
142          - description: Address and length of RX2.
143
144      '#clock-cells':
145        const: 1
146
147      '#phy-cells':
148        const: 0
149
150    required:
151      - reg
152      - '#clock-cells'
153      - '#phy-cells'
154
155required:
156  - compatible
157  - reg
158  - "#address-cells"
159  - "#size-cells"
160  - ranges
161  - clocks
162  - clock-names
163  - resets
164  - reset-names
165  - vdda-phy-supply
166  - vdda-pll-supply
167
168allOf:
169  - if:
170      properties:
171        compatible:
172          enum:
173            - qcom,sc7180-qmp-usb3-dp-phy
174            - qcom,sdm845-qmp-usb3-dp-phy
175    then:
176      properties:
177        clocks:
178          items:
179            - description: Phy aux clock
180            - description: Phy config clock
181            - description: 19.2 MHz ref clk
182            - description: Phy common block aux clock
183        clock-names:
184          items:
185            - const: aux
186            - const: cfg_ahb
187            - const: ref
188            - const: com_aux
189
190  - if:
191      properties:
192        compatible:
193          enum:
194            - qcom,sc8180x-qmp-usb3-dp-phy
195    then:
196      properties:
197        clocks:
198          items:
199            - description: Phy aux clock
200            - description: 19.2 MHz ref clk
201            - description: Phy common block aux clock
202        clock-names:
203          items:
204            - const: aux
205            - const: ref
206            - const: com_aux
207
208  - if:
209      properties:
210        compatible:
211          enum:
212            - qcom,sm8250-qmp-usb3-dp-phy
213    then:
214      properties:
215        clocks:
216          items:
217            - description: Phy aux clock
218            - description: Board XO source
219            - description: Phy common block aux clock
220        clock-names:
221          items:
222            - const: aux
223            - const: ref_clk_src
224            - const: com_aux
225
226additionalProperties: false
227
228examples:
229  - |
230    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
231    usb_1_qmpphy: phy-wrapper@88e9000 {
232        compatible = "qcom,sdm845-qmp-usb3-dp-phy";
233        reg = <0x088e9000 0x18c>,
234              <0x088e8000 0x10>,
235              <0x088ea000 0x40>;
236        reg-names = "usb", "dp_com", "dp";
237        #address-cells = <1>;
238        #size-cells = <1>;
239        ranges = <0x0 0x088e9000 0x2000>;
240
241        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
242                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
243                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
244                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
245        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
246
247        resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
248                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
249        reset-names = "phy", "common";
250
251        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
252        vdda-pll-supply = <&vdda_usb2_ss_core>;
253
254        usb3-phy@200 {
255            reg = <0x200 0x128>,
256                  <0x400 0x200>,
257                  <0xc00 0x218>,
258                  <0x600 0x128>,
259                  <0x800 0x200>,
260                  <0xa00 0x100>;
261            #clock-cells = <0>;
262            #phy-cells = <0>;
263            clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
264            clock-output-names = "usb3_phy_pipe_clk_src";
265        };
266
267        dp-phy@88ea200 {
268            reg = <0xa200 0x200>,
269                  <0xa400 0x200>,
270                  <0xaa00 0x200>,
271                  <0xa600 0x200>,
272                  <0xa800 0x200>;
273            #clock-cells = <1>;
274            #phy-cells = <0>;
275        };
276    };
277