1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E WIZ (SERDES Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    enum:
16      - ti,j721e-wiz-16g
17      - ti,j721e-wiz-10g
18      - ti,j721s2-wiz-10g
19      - ti,am64-wiz-10g
20      - ti,j7200-wiz-10g
21      - ti,j784s4-wiz-10g
22
23  power-domains:
24    maxItems: 1
25
26  clocks:
27    minItems: 3
28    maxItems: 4
29    description: clock-specifier to represent input to the WIZ
30
31  clock-names:
32    minItems: 3
33    items:
34      - const: fck
35      - const: core_ref_clk
36      - const: ext_ref_clk
37      - const: core_ref1_clk
38
39  num-lanes:
40    minimum: 1
41    maximum: 4
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  "#reset-cells":
50    const: 1
51
52  "#clock-cells":
53    const: 1
54
55  ranges: true
56
57  assigned-clocks:
58    minItems: 1
59    maxItems: 2
60
61  assigned-clock-parents:
62    minItems: 1
63    maxItems: 2
64
65  assigned-clock-rates:
66    minItems: 1
67    maxItems: 2
68
69  typec-dir-gpios:
70    maxItems: 1
71    description:
72      GPIO to signal Type-C cable orientation for lane swap.
73      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
74      achieve the funtionality of an external type-C plug flip mux.
75
76  typec-dir-debounce-ms:
77    minimum: 100
78    maximum: 1000
79    default: 100
80    description:
81      Number of milliseconds to wait before sampling typec-dir-gpio.
82      If not specified, the default debounce of 100ms will be used.
83      Type-C spec states minimum CC pin debounce of 100 ms and maximum
84      of 200 ms. However, some solutions might need more than 200 ms.
85
86  refclk-dig:
87    type: object
88    additionalProperties: false
89    description: |
90      WIZ node should have subnode for refclk_dig to select the reference
91      clock source for the reference clock used in the PHY and PMA digital
92      logic.
93    deprecated: true
94    properties:
95      clocks:
96        minItems: 2
97        maxItems: 4
98        description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
99          the inputs to refclk_dig
100
101      "#clock-cells":
102        const: 0
103
104      assigned-clocks:
105        maxItems: 1
106
107      assigned-clock-parents:
108        maxItems: 1
109
110    required:
111      - clocks
112      - "#clock-cells"
113      - assigned-clocks
114      - assigned-clock-parents
115
116  ti,scm:
117    $ref: /schemas/types.yaml#/definitions/phandle
118    description: |
119      phandle to System Control Module for syscon regmap access.
120
121patternProperties:
122  "^pll[0|1]-refclk$":
123    type: object
124    additionalProperties: false
125    description: |
126      WIZ node should have subnodes for each of the PLLs present in
127      the SERDES.
128    deprecated: true
129    properties:
130      clocks:
131        maxItems: 2
132        description: Phandle to clock nodes representing the two inputs to PLL.
133
134      "#clock-cells":
135        const: 0
136
137      assigned-clocks:
138        maxItems: 1
139
140      assigned-clock-parents:
141        maxItems: 1
142
143    required:
144      - clocks
145      - "#clock-cells"
146      - assigned-clocks
147      - assigned-clock-parents
148
149  "^cmn-refclk1?-dig-div$":
150    type: object
151    additionalProperties: false
152    description:
153      WIZ node should have subnodes for each of the PMA common refclock
154      provided by the SERDES.
155    deprecated: true
156    properties:
157      clocks:
158        maxItems: 1
159        description: Phandle to the clock node representing the input to the
160          divider clock.
161
162      "#clock-cells":
163        const: 0
164
165    required:
166      - clocks
167      - "#clock-cells"
168
169  "^serdes@[0-9a-f]+$":
170    type: object
171    description: |
172      WIZ node should have '1' subnode for the SERDES. It could be either
173      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
174      bindings specified in
175      Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
176      Torrent SERDES should follow the bindings specified in
177      Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
178
179required:
180  - compatible
181  - power-domains
182  - clocks
183  - clock-names
184  - num-lanes
185  - "#address-cells"
186  - "#size-cells"
187  - "#reset-cells"
188  - ranges
189
190allOf:
191  - if:
192      properties:
193        compatible:
194          contains:
195            const: ti,j7200-wiz-10g
196    then:
197      required:
198        - ti,scm
199
200additionalProperties: false
201
202examples:
203  - |
204    #include <dt-bindings/soc/ti,sci_pm_domain.h>
205
206    wiz@5000000 {
207           compatible = "ti,j721e-wiz-16g";
208           #address-cells = <1>;
209           #size-cells = <1>;
210           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
211           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
212           clock-names = "fck", "core_ref_clk", "ext_ref_clk";
213           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
214           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
215           num-lanes = <2>;
216           #reset-cells = <1>;
217           ranges = <0x5000000 0x5000000 0x10000>;
218
219           pll0-refclk {
220                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
221                  #clock-cells = <0>;
222                  assigned-clocks = <&wiz1_pll0_refclk>;
223                  assigned-clock-parents = <&k3_clks 293 13>;
224           };
225
226           pll1-refclk {
227                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
228                  #clock-cells = <0>;
229                  assigned-clocks = <&wiz1_pll1_refclk>;
230                  assigned-clock-parents = <&k3_clks 293 0>;
231           };
232
233           cmn-refclk-dig-div {
234                  clocks = <&wiz1_refclk_dig>;
235                  #clock-cells = <0>;
236           };
237
238           cmn-refclk1-dig-div {
239                  clocks = <&wiz1_pll1_refclk>;
240                  #clock-cells = <0>;
241           };
242
243           refclk-dig {
244                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
245                          <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
246                  #clock-cells = <0>;
247                  assigned-clocks = <&wiz0_refclk_dig>;
248                  assigned-clock-parents = <&k3_clks 292 11>;
249           };
250
251           serdes@5000000 {
252                  compatible = "ti,sierra-phy-t0";
253                  reg-names = "serdes";
254                  reg = <0x5000000 0x10000>;
255                  #address-cells = <1>;
256                  #size-cells = <0>;
257                  resets = <&serdes_wiz0 0>;
258                  reset-names = "sierra_reset";
259                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
260                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
261           };
262    };
263