1* Atmel AT91 Pinmux Controller
2
3The AT91 Pinmux Controller, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
68 muxing options (called periph modes). Since different modules require
7different PAD settings (like pull up, keeper, etc) the controller controls
8also the PAD settings parameters.
9
10Please refer to pinctrl-bindings.txt in this directory for details of the
11common pinctrl bindings used by client devices, including the meaning of the
12phrase "pin configuration node".
13
14Atmel AT91 pin configuration node is a node of a group of pins which can be
15used for a specific device or function. This node represents both mux and config
16of the pins in that group. The 'pins' selects the function mode(also named pin
17mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, multi drive, etc.
19
20Required properties for iomux controller:
21- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22		or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
24  configured in this periph mode. All the periph and bank need to be describe.
25
26How to create such array:
27
28Each column will represent the possible peripheral of the pinctrl
29Each line will represent a pio bank
30
31Take an example on the 9260
32Peripheral: 2 ( A and B)
33Bank: 3 (A, B and C)
34=>
35
36  /*    A         B     */
37  0xffffffff 0xffc00c3b  /* pioA */
38  0xffffffff 0x7fff3ccf  /* pioB */
39  0xffffffff 0x007fffff  /* pioC */
40
41For each peripheral/bank we will describe in a u32 if a pin can be
42configured in it by putting 1 to the pin bit (1 << pin)
43
44Let's take the pioA on peripheral B
45From the datasheet Table 10-2.
46Peripheral B
47PA0	MCDB0
48PA1	MCCDB
49PA2
50PA3	MCDB3
51PA4	MCDB2
52PA5	MCDB1
53PA6
54PA7
55PA8
56PA9
57PA10	ETX2
58PA11	ETX3
59PA12
60PA13
61PA14
62PA15
63PA16
64PA17
65PA18
66PA19
67PA20
68PA21
69PA22	ETXER
70PA23	ETX2
71PA24	ETX3
72PA25	ERX2
73PA26	ERX3
74PA27	ERXCK
75PA28	ECRS
76PA29	ECOL
77PA30	RXD4
78PA31	TXD4
79
80=> 0xffc00c3b
81
82Required properties for pin configuration node:
83- atmel,pins: 4 integers array, represents a group of pins mux and config
84  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
85  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
86  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
87
88Bits used for CONFIG:
89PULL_UP		(1 << 0): indicate this pin needs a pull up.
90MULTIDRIVE	(1 << 1): indicate this pin needs to be configured as multi-drive.
91			Multi-drive is equivalent to open-drain type output.
92DEGLITCH	(1 << 2): indicate this pin needs deglitch.
93PULL_DOWN	(1 << 3): indicate this pin needs a pull down.
94DIS_SCHMIT	(1 << 4): indicate this pin needs to the disable schmitt trigger.
95DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
96			following values:
97				00 - No change (reset state value kept)
98				01 - Low
99				10 - Medium
100				11 - High
101OUTPUT		(1 << 7): indicate this pin need to be configured as an output.
102OUTPUT_VAL	(1 << 8): output val (1 = high, 0 = low)
103SLEWRATE	(1 << 9): slew rate of the pin: 0 = disable, 1 = enable
104DEBOUNCE	(1 << 16): indicate this pin needs debounce.
105DEBOUNCE_VAL	(0x3fff << 17): debounce value.
106
107NOTE:
108Some requirements for using atmel,at91rm9200-pinctrl binding:
1091. We have pin function node defined under at91 controller node to represent
110   what pinmux functions this SoC supports.
1112. The driver can use the function node's name and pin configuration node's
112   name describe the pin function and group hierarchy.
113   For example, Linux at91 pinctrl driver takes the function node's name
114   as the function name and pin configuration node's name as group name to
115   create the map table.
1163. Each pin configuration node should have a phandle, devices can set pins
117   configurations by referring to the phandle of that pin configuration node.
1184. The gpio controller must be describe in the pinctrl simple-bus.
119
120For each bank the required properties are:
121- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
122  "microchip,sam9x60-gpio"
123- reg: physical base address and length of the controller's registers
124- interrupts: interrupt outputs from the controller
125- interrupt-controller: marks the device node as an interrupt controller
126- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
127  for more details.
128- gpio-controller
129- #gpio-cells: should be 2; the first cell is the GPIO number and the second
130  cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
131- clocks: bank clock
132
133Examples:
134
135pinctrl@fffff400 {
136	#address-cells = <1>;
137	#size-cells = <1>;
138	ranges;
139	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
140	reg = <0xfffff400 0x600>;
141
142	pioA: gpio@fffff400 {
143		compatible = "atmel,at91sam9x5-gpio";
144		reg = <0xfffff400 0x200>;
145		interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
146		#gpio-cells = <2>;
147		gpio-controller;
148		interrupt-controller;
149		#interrupt-cells = <2>;
150		clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
151	};
152
153	atmel,mux-mask = <
154	      /*    A         B     */
155	       0xffffffff 0xffc00c3b  /* pioA */
156	       0xffffffff 0x7fff3ccf  /* pioB */
157	       0xffffffff 0x007fffff  /* pioC */
158	      >;
159
160	/* shared pinctrl settings */
161	dbgu {
162		pinctrl_dbgu: dbgu-0 {
163			atmel,pins =
164				<1 14 0x1 0x0	/* PB14 periph A */
165				 1 15 0x1 0x1>;	/* PB15 periph A with pullup */
166		};
167	};
168};
169
170dbgu: serial@fffff200 {
171	compatible = "atmel,at91sam9260-usart";
172	reg = <0xfffff200 0x200>;
173	interrupts = <1 4 7>;
174	pinctrl-names = "default";
175	pinctrl-0 = <&pinctrl_dbgu>;
176};
177