1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/serial/renesas,scifb.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Renesas Serial Communications Interface with FIFO B (SCIFB) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12allOf: 13 - $ref: serial.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - renesas,scifb-r8a73a4 # R-Mobile APE6 21 - renesas,scifb-r8a7740 # R-Mobile A1 22 - renesas,scifb-sh73a0 # SH-Mobile AG5 23 - const: renesas,scifb # generic SCIFB compatible UART 24 25 - items: 26 - enum: 27 - renesas,scifb-r8a7742 # RZ/G1H 28 - renesas,scifb-r8a7743 # RZ/G1M 29 - renesas,scifb-r8a7744 # RZ/G1N 30 - renesas,scifb-r8a7745 # RZ/G1E 31 - renesas,scifb-r8a7790 # R-Car H2 32 - renesas,scifb-r8a7791 # R-Car M2-W 33 - renesas,scifb-r8a7793 # R-Car M2-N 34 - renesas,scifb-r8a7794 # R-Car E2 35 - const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1 36 - const: renesas,scifb # generic SCIFB compatible UART 37 38 reg: 39 maxItems: 1 40 41 interrupts: 42 maxItems: 1 43 44 clocks: 45 maxItems: 1 46 47 clock-names: 48 enum: 49 - fck # UART functional clock 50 51 power-domains: 52 maxItems: 1 53 54 resets: 55 maxItems: 1 56 57 dmas: 58 minItems: 2 59 maxItems: 4 60 description: 61 Must contain a list of pairs of references to DMA specifiers, one for 62 transmission, and one for reception. 63 64 dma-names: 65 minItems: 2 66 maxItems: 4 67 items: 68 enum: 69 - tx 70 - rx 71 72required: 73 - compatible 74 - reg 75 - interrupts 76 - clocks 77 - clock-names 78 - power-domains 79 80unevaluatedProperties: false 81 82if: 83 properties: 84 compatible: 85 contains: 86 enum: 87 - renesas,rcar-gen2-scifb 88then: 89 required: 90 - resets 91 92examples: 93 - | 94 #include <dt-bindings/clock/r8a7740-clock.h> 95 #include <dt-bindings/interrupt-controller/arm-gic.h> 96 scifb: serial@e6c30000 { 97 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 98 reg = <0xe6c30000 0x100>; 99 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 101 clock-names = "fck"; 102 power-domains = <&pd_a3sp>; 103 }; 104