1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
12
13description: |+
14  Each Samsung UART should have an alias correctly numbered in the "aliases"
15  node, according to serialN format, where N is the port number (non-negative
16  decimal integer) as specified by User's Manual of respective SoC.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - const: samsung,exynosautov9-uart
23          - const: samsung,exynos850-uart
24      - enum:
25          - apple,s5l-uart
26          - axis,artpec8-uart
27          - samsung,s3c2410-uart
28          - samsung,s3c2412-uart
29          - samsung,s3c2440-uart
30          - samsung,s3c6400-uart
31          - samsung,s5pv210-uart
32          - samsung,exynos4210-uart
33          - samsung,exynos5433-uart
34          - samsung,exynos850-uart
35
36  reg:
37    maxItems: 1
38
39  reg-io-width:
40    description: |
41      The size (in bytes) of the IO accesses that should be performed
42      on the device.
43    enum: [ 1, 4 ]
44
45  clocks:
46    minItems: 2
47    maxItems: 5
48
49  clock-names:
50    description: N = 0 is allowed for SoCs without internal baud clock mux.
51    minItems: 2
52    items:
53      - const: uart
54      - pattern: '^clk_uart_baud[0-3]$'
55      - pattern: '^clk_uart_baud[0-3]$'
56      - pattern: '^clk_uart_baud[0-3]$'
57      - pattern: '^clk_uart_baud[0-3]$'
58
59  dmas:
60    items:
61      - description: DMA controller phandle and request line for RX
62      - description: DMA controller phandle and request line for TX
63
64  dma-names:
65    items:
66      - const: rx
67      - const: tx
68
69  interrupts:
70    description: RX interrupt and optionally TX interrupt.
71    minItems: 1
72    maxItems: 2
73
74  power-domains:
75    maxItems: 1
76
77  samsung,uart-fifosize:
78    description: The fifo size supported by the UART channel.
79    $ref: /schemas/types.yaml#/definitions/uint32
80    enum: [16, 64, 256]
81
82required:
83  - compatible
84  - clocks
85  - clock-names
86  - interrupts
87  - reg
88
89unevaluatedProperties: false
90
91allOf:
92  - $ref: serial.yaml#
93
94  - if:
95      properties:
96        compatible:
97          contains:
98            enum:
99              - samsung,s3c2410-uart
100              - samsung,s5pv210-uart
101    then:
102      properties:
103        clocks:
104          minItems: 2
105          maxItems: 3
106        clock-names:
107          minItems: 2
108          items:
109            - const: uart
110            - pattern: '^clk_uart_baud[0-1]$'
111            - pattern: '^clk_uart_baud[0-1]$'
112
113  - if:
114      properties:
115        compatible:
116          contains:
117            enum:
118              - apple,s5l-uart
119              - axis,artpec8-uart
120              - samsung,exynos4210-uart
121              - samsung,exynos5433-uart
122    then:
123      properties:
124        clocks:
125          maxItems: 2
126        clock-names:
127          items:
128            - const: uart
129            - const: clk_uart_baud0
130
131examples:
132  - |
133    #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
134
135    uart0: serial@7f005000 {
136        compatible = "samsung,s3c6400-uart";
137        reg = <0x7f005000 0x100>;
138        interrupt-parent = <&vic1>;
139        interrupts = <5>;
140        clock-names = "uart", "clk_uart_baud2",
141                      "clk_uart_baud3";
142        clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
143                 <&clocks SCLK_UART>;
144        samsung,uart-fifosize = <16>;
145    };
146