1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24  their implementation lacks a memory-mapped MTIME register, thus not
25  compatible with SiFive ones.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - sifive,fu540-c000-clint
33              - starfive,jh7100-clint
34              - canaan,k210-clint
35          - const: sifive,clint0
36      - items:
37          - enum:
38              - allwinner,sun20i-d1-clint
39          - const: thead,c900-clint
40      - items:
41          - const: sifive,clint0
42          - const: riscv,clint0
43        deprecated: true
44        description: For the QEMU virt machine only
45
46    description:
47      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
48      Supported compatible strings are -
49      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
50      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
51      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
52      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
53      integration tweaks.
54      Please refer to sifive-blocks-ip-versioning.txt for details
55
56  reg:
57    maxItems: 1
58
59  interrupts-extended:
60    minItems: 1
61    maxItems: 4095
62
63additionalProperties: false
64
65required:
66  - compatible
67  - reg
68  - interrupts-extended
69
70examples:
71  - |
72    timer@2000000 {
73      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
74      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
75                            <&cpu2intc 3>, <&cpu2intc 7>,
76                            <&cpu3intc 3>, <&cpu3intc 7>,
77                            <&cpu4intc 3>, <&cpu4intc 7>;
78       reg = <0x2000000 0x10000>;
79    };
80...
81