1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/*
7 * AM335x ICE V2 board
8 * http://www.ti.com/tool/tmdsice3359
9 */
10
11/dts-v1/;
12
13#include "am33xx.dtsi"
14
15/ {
16	model = "TI AM3359 ICE-V2";
17	compatible = "ti,am3359-icev2", "ti,am33xx";
18
19	memory@80000000 {
20		device_type = "memory";
21		reg = <0x80000000 0x10000000>; /* 256 MB */
22	};
23
24	chosen {
25		stdout-path = &uart3;
26	};
27
28	vbat: fixedregulator0 {
29		compatible = "regulator-fixed";
30		regulator-name = "vbat";
31		regulator-min-microvolt = <5000000>;
32		regulator-max-microvolt = <5000000>;
33		regulator-boot-on;
34	};
35
36	vtt_fixed: fixedregulator1 {
37		compatible = "regulator-fixed";
38		regulator-name = "vtt";
39		regulator-min-microvolt = <1500000>;
40		regulator-max-microvolt = <1500000>;
41		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
42		regulator-always-on;
43		regulator-boot-on;
44		enable-active-high;
45	};
46
47	leds-iio {
48		status = "disabled";
49		compatible = "gpio-leds";
50		led-out0 {
51			label = "out0";
52			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
53			default-state = "off";
54		};
55
56		led-out1 {
57			label = "out1";
58			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
59			default-state = "off";
60		};
61
62		led-out2 {
63			label = "out2";
64			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
65			default-state = "off";
66		};
67
68		led-out3 {
69			label = "out3";
70			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
71			default-state = "off";
72		};
73
74		led-out4 {
75			label = "out4";
76			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
77			default-state = "off";
78		};
79
80		led-out5 {
81			label = "out5";
82			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
83			default-state = "off";
84		};
85
86		led-out6 {
87			label = "out6";
88			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
89			default-state = "off";
90		};
91
92		led-out7 {
93			label = "out7";
94			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
95			default-state = "off";
96		};
97	};
98
99	/* Tricolor status LEDs */
100	leds1 {
101		compatible = "gpio-leds";
102		pinctrl-names = "default";
103		pinctrl-0 = <&user_leds>;
104
105		led0 {
106			label = "status0:red:cpu0";
107			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
108			default-state = "off";
109			linux,default-trigger = "cpu0";
110		};
111
112		led1 {
113			label = "status0:green:usr";
114			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
115			default-state = "off";
116		};
117
118		led2 {
119			label = "status0:yellow:usr";
120			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
121			default-state = "off";
122		};
123
124		led3 {
125			label = "status1:red:mmc0";
126			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
127			default-state = "off";
128			linux,default-trigger = "mmc0";
129		};
130
131		led4 {
132			label = "status1:green:usr";
133			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
134			default-state = "off";
135		};
136
137		led5 {
138			label = "status1:yellow:usr";
139			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
140			default-state = "off";
141		};
142	};
143	gpio-decoder {
144		compatible = "gpio-decoder";
145		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
146			<&pca9536 2 GPIO_ACTIVE_HIGH>,
147			<&pca9536 1 GPIO_ACTIVE_HIGH>,
148			<&pca9536 0 GPIO_ACTIVE_HIGH>;
149		linux,axis = <0>; /* ABS_X */
150		decoder-max-value = <9>;
151	};
152};
153
154&am33xx_pinmux {
155	user_leds: user_leds {
156		pinctrl-single,pins = <
157			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
158			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
159			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
160			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
161			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
162			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
163		>;
164	};
165
166	mmc0_pins_default: mmc0_pins_default {
167		pinctrl-single,pins = <
168			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
169			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
170			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
171			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
172			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
173			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
174		>;
175	};
176
177	i2c0_pins_default: i2c0_pins_default {
178		pinctrl-single,pins = <
179			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
180			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
181		>;
182	};
183
184	spi0_pins_default: spi0_pins_default {
185		pinctrl-single,pins = <
186			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
187			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
188			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
189			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
190			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)
191			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
192		>;
193	};
194
195	uart3_pins_default: uart3_pins_default {
196		pinctrl-single,pins = <
197			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
198			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
199		>;
200	};
201
202	cpsw_default: cpsw_default {
203		pinctrl-single,pins = <
204			/* Slave 1, RMII mode */
205			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
206			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
207			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
208			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
209			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
210			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
211			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
212			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txen.rmii1_txen */
213			/* Slave 2, RMII mode */
214			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wait0.rmii2_crs_dv */
215			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_col.rmii2_refclk */
216			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a11.rmii2_rxd0 */
217			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a10.rmii2_rxd1 */
218			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wpn.rmii2_rxerr */
219			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a5.rmii2_txd0 */
220			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a4.rmii2_txd1 */
221			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a0.rmii2_txen */
222		>;
223	};
224
225	cpsw_sleep: cpsw_sleep {
226		pinctrl-single,pins = <
227			/* Slave 1 reset value */
228			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
229			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
230			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
231			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
232			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
233			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
234			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
235			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
236
237			/* Slave 2 reset value */
238			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
239			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
240			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
241			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
242			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
243			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
244			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
245			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
246		>;
247	};
248
249	davinci_mdio_default: davinci_mdio_default {
250		pinctrl-single,pins = <
251			/* MDIO */
252			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
253			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
254		>;
255	};
256
257	davinci_mdio_sleep: davinci_mdio_sleep {
258		pinctrl-single,pins = <
259			/* MDIO reset value */
260			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
261			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
262		>;
263	};
264};
265
266&i2c0 {
267	pinctrl-names = "default";
268	pinctrl-0 = <&i2c0_pins_default>;
269
270	status = "okay";
271	clock-frequency = <400000>;
272
273	tps: power-controller@2d {
274		reg = <0x2d>;
275	};
276
277	tpic2810: gpio@60 {
278		compatible = "ti,tpic2810";
279		reg = <0x60>;
280		gpio-controller;
281		#gpio-cells = <2>;
282	};
283
284	pca9536: gpio@41 {
285		compatible = "ti,pca9536";
286		reg = <0x41>;
287		gpio-controller;
288		#gpio-cells = <2>;
289	};
290
291	/* osd9616p0899-10 */
292	display@3c {
293		compatible = "solomon,ssd1306fb-i2c";
294		reg = <0x3c>;
295		solomon,height = <16>;
296		solomon,width = <96>;
297		solomon,com-seq;
298		solomon,com-invdir;
299		solomon,page-offset = <0>;
300		solomon,prechargep1 = <2>;
301		solomon,prechargep2 = <13>;
302	};
303};
304
305&spi0 {
306	status = "okay";
307	pinctrl-names = "default";
308	pinctrl-0 = <&spi0_pins_default>;
309
310	sn65hvs882@1 {
311		compatible = "pisosr-gpio";
312		gpio-controller;
313		#gpio-cells = <2>;
314
315		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
316
317		reg = <1>;
318		spi-max-frequency = <1000000>;
319		spi-cpol;
320	};
321
322	spi_nor: flash@0 {
323		#address-cells = <1>;
324		#size-cells = <1>;
325		compatible = "winbond,w25q64", "jedec,spi-nor";
326		spi-max-frequency = <80000000>;
327		m25p,fast-read;
328		reg = <0>;
329
330		partition@0 {
331			label = "u-boot-spl";
332			reg = <0x0 0x80000>;
333			read-only;
334		};
335
336		partition@1 {
337			label = "u-boot";
338			reg = <0x80000 0x100000>;
339			read-only;
340		};
341
342		partition@2 {
343			label = "u-boot-env";
344			reg = <0x180000 0x20000>;
345			read-only;
346		};
347
348		partition@3 {
349			label = "misc";
350			reg = <0x1A0000 0x660000>;
351		};
352	};
353
354};
355
356&tscadc {
357	status = "okay";
358	adc {
359		ti,adc-channels = <1 2 3 4 5 6 7>;
360	};
361};
362
363#include "tps65910.dtsi"
364
365&tps {
366	vcc1-supply = <&vbat>;
367	vcc2-supply = <&vbat>;
368	vcc3-supply = <&vbat>;
369	vcc4-supply = <&vbat>;
370	vcc5-supply = <&vbat>;
371	vcc6-supply = <&vbat>;
372	vcc7-supply = <&vbat>;
373	vccio-supply = <&vbat>;
374
375	regulators {
376		vrtc_reg: regulator@0 {
377			regulator-always-on;
378		};
379
380		vio_reg: regulator@1 {
381			regulator-always-on;
382		};
383
384		vdd1_reg: regulator@2 {
385			regulator-name = "vdd_mpu";
386			regulator-min-microvolt = <912500>;
387			regulator-max-microvolt = <1326000>;
388			regulator-boot-on;
389			regulator-always-on;
390		};
391
392		vdd2_reg: regulator@3 {
393			regulator-name = "vdd_core";
394			regulator-min-microvolt = <912500>;
395			regulator-max-microvolt = <1144000>;
396			regulator-boot-on;
397			regulator-always-on;
398		};
399
400		vdd3_reg: regulator@4 {
401			regulator-always-on;
402		};
403
404		vdig1_reg: regulator@5 {
405			regulator-always-on;
406		};
407
408		vdig2_reg: regulator@6 {
409			regulator-always-on;
410		};
411
412		vpll_reg: regulator@7 {
413			regulator-always-on;
414		};
415
416		vdac_reg: regulator@8 {
417			regulator-always-on;
418		};
419
420		vaux1_reg: regulator@9 {
421			regulator-always-on;
422		};
423
424		vaux2_reg: regulator@10 {
425			regulator-always-on;
426		};
427
428		vaux33_reg: regulator@11 {
429			regulator-always-on;
430		};
431
432		vmmc_reg: regulator@12 {
433			regulator-min-microvolt = <1800000>;
434			regulator-max-microvolt = <3300000>;
435			regulator-always-on;
436		};
437	};
438};
439
440&mmc1 {
441	status = "okay";
442	vmmc-supply = <&vmmc_reg>;
443	bus-width = <4>;
444	pinctrl-names = "default";
445	pinctrl-0 = <&mmc0_pins_default>;
446};
447
448&gpio0_target {
449	/* Do not idle the GPIO used for holding the VTT regulator */
450	ti,no-reset-on-init;
451	ti,no-idle-on-init;
452};
453
454&uart3 {
455	pinctrl-names = "default";
456	pinctrl-0 = <&uart3_pins_default>;
457	status = "okay";
458};
459
460&gpio3 {
461	pr1-mii-ctl-hog {
462		gpio-hog;
463		gpios = <4 GPIO_ACTIVE_HIGH>;
464		output-high;
465		line-name = "PR1_MII_CTRL";
466	};
467
468	mux-mii-hog {
469		gpio-hog;
470		gpios = <10 GPIO_ACTIVE_HIGH>;
471		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
472		output-high;
473		line-name = "MUX_MII_CTL1";
474	};
475};
476
477&cpsw_port1 {
478	phy-handle = <&ethphy0>;
479	phy-mode = "rmii";
480	ti,dual-emac-pvid = <1>;
481};
482
483&cpsw_port2 {
484	phy-handle = <&ethphy1>;
485	phy-mode = "rmii";
486	ti,dual-emac-pvid = <2>;
487};
488
489&mac_sw {
490	pinctrl-names = "default", "sleep";
491	pinctrl-0 = <&cpsw_default>;
492	pinctrl-1 = <&cpsw_sleep>;
493	status = "okay";
494};
495
496&davinci_mdio_sw {
497	pinctrl-names = "default", "sleep";
498	pinctrl-0 = <&davinci_mdio_default>;
499	pinctrl-1 = <&davinci_mdio_sleep>;
500	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
501	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
502
503	ethphy0: ethernet-phy@1 {
504		reg = <1>;
505	};
506
507	ethphy1: ethernet-phy@3 {
508		reg = <3>;
509	};
510};
511
512&pruss_tm {
513	status = "okay";
514};
515
516&rtc {
517	system-power-controller;
518};
519