1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10	compatible = "brcm,bcm6756", "brcm,bcmbca";
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	interrupt-parent = <&gic>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		CA7_0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a7";
23			reg = <0x0>;
24			next-level-cache = <&L2_0>;
25			enable-method = "psci";
26		};
27
28		CA7_1: cpu@1 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x1>;
32			next-level-cache = <&L2_0>;
33			enable-method = "psci";
34		};
35
36		CA7_2: cpu@2 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a7";
39			reg = <0x2>;
40			next-level-cache = <&L2_0>;
41			enable-method = "psci";
42		};
43
44		CA7_3: cpu@3 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a7";
47			reg = <0x3>;
48			next-level-cache = <&L2_0>;
49			enable-method = "psci";
50		};
51
52		L2_0: l2-cache0 {
53			compatible = "cache";
54			cache-level = <2>;
55		};
56	};
57
58	timer {
59		compatible = "arm,armv7-timer";
60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
64		arm,cpu-registers-not-fw-configured;
65	};
66
67	pmu: pmu {
68		compatible = "arm,cortex-a7-pmu";
69		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
70			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
72			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
73		interrupt-affinity = <&CA7_0>, <&CA7_1>,
74			<&CA7_2>, <&CA7_3>;
75	};
76
77	clocks: clocks {
78		periph_clk: periph-clk {
79			compatible = "fixed-clock";
80			#clock-cells = <0>;
81			clock-frequency = <200000000>;
82		};
83
84		uart_clk: uart-clk {
85			compatible = "fixed-factor-clock";
86			#clock-cells = <0>;
87			clocks = <&periph_clk>;
88			clock-div = <4>;
89			clock-mult = <1>;
90		};
91	};
92
93	psci {
94		compatible = "arm,psci-0.2";
95		method = "smc";
96	};
97
98	axi@81000000 {
99		compatible = "simple-bus";
100		#address-cells = <1>;
101		#size-cells = <1>;
102		ranges = <0 0x81000000 0x8000>;
103
104		gic: interrupt-controller@1000 {
105			compatible = "arm,cortex-a7-gic";
106			#interrupt-cells = <3>;
107			interrupt-controller;
108			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109			reg = <0x1000 0x1000>,
110				<0x2000 0x2000>,
111				<0x4000 0x2000>,
112				<0x6000 0x2000>;
113		};
114	};
115
116	bus@ff800000 {
117		compatible = "simple-bus";
118		#address-cells = <1>;
119		#size-cells = <1>;
120		ranges = <0 0xff800000 0x800000>;
121
122		uart0: serial@12000 {
123			compatible = "arm,pl011", "arm,primecell";
124			reg = <0x12000 0x1000>;
125			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
126			clocks = <&uart_clk>, <&uart_clk>;
127			clock-names = "uartclk", "apb_pclk";
128			status = "disabled";
129		};
130	};
131};
132