1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "brcm,bcm6855", "brcm,bcmbca"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 CA7_0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a7"; 23 reg = <0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 CA7_1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 CA7_2: cpu@2 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a7"; 39 reg = <0x2>; 40 next-level-cache = <&L2_0>; 41 enable-method = "psci"; 42 }; 43 44 L2_0: l2-cache0 { 45 compatible = "cache"; 46 cache-level = <2>; 47 }; 48 }; 49 50 timer { 51 compatible = "arm,armv7-timer"; 52 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, 55 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; 56 arm,cpu-registers-not-fw-configured; 57 }; 58 59 pmu: pmu { 60 compatible = "arm,cortex-a7-pmu"; 61 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 64 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; 65 }; 66 67 clocks: clocks { 68 periph_clk: periph-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <200000000>; 72 }; 73 74 uart_clk: uart-clk { 75 compatible = "fixed-factor-clock"; 76 #clock-cells = <0>; 77 clocks = <&periph_clk>; 78 clock-div = <4>; 79 clock-mult = <1>; 80 }; 81 }; 82 83 psci { 84 compatible = "arm,psci-0.2"; 85 method = "smc"; 86 }; 87 88 axi@81000000 { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0x81000000 0x8000>; 93 94 gic: interrupt-controller@1000 { 95 compatible = "arm,cortex-a7-gic"; 96 #interrupt-cells = <3>; 97 interrupt-controller; 98 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; 99 reg = <0x1000 0x1000>, 100 <0x2000 0x2000>, 101 <0x4000 0x2000>, 102 <0x6000 0x2000>; 103 }; 104 }; 105 106 bus@ff800000 { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0xff800000 0x800000>; 111 112 uart0: serial@12000 { 113 compatible = "arm,pl011", "arm,primecell"; 114 reg = <0x12000 0x1000>; 115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&uart_clk>, <&uart_clk>; 117 clock-names = "uartclk", "apb_pclk"; 118 status = "disabled"; 119 }; 120 }; 121}; 122