1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4.dtsi"
18
19#include "exynos4-cpu-thermal.dtsi"
20
21/ {
22	compatible = "samsung,exynos4412", "samsung,exynos4";
23
24	aliases {
25		pinctrl0 = &pinctrl_0;
26		pinctrl1 = &pinctrl_1;
27		pinctrl2 = &pinctrl_2;
28		pinctrl3 = &pinctrl_3;
29		fimc-lite0 = &fimc_lite_0;
30		fimc-lite1 = &fimc_lite_1;
31		mshc0 = &mshc_0;
32	};
33
34	bus_acp: bus-acp {
35		compatible = "samsung,exynos-bus";
36		clocks = <&clock CLK_DIV_ACP>;
37		clock-names = "bus";
38		operating-points-v2 = <&bus_acp_opp_table>;
39		status = "disabled";
40
41		bus_acp_opp_table: opp-table {
42			compatible = "operating-points-v2";
43
44			opp-100000000 {
45				opp-hz = /bits/ 64 <100000000>;
46			};
47			opp-134000000 {
48				opp-hz = /bits/ 64 <134000000>;
49			};
50			opp-160000000 {
51				opp-hz = /bits/ 64 <160000000>;
52			};
53			opp-267000000 {
54				opp-hz = /bits/ 64 <267000000>;
55			};
56		};
57	};
58
59	bus_c2c: bus-c2c {
60		compatible = "samsung,exynos-bus";
61		clocks = <&clock CLK_DIV_C2C>;
62		clock-names = "bus";
63		operating-points-v2 = <&bus_dmc_opp_table>;
64		status = "disabled";
65	};
66
67	bus_dmc: bus-dmc {
68		compatible = "samsung,exynos-bus";
69		clocks = <&clock CLK_DIV_DMC>;
70		clock-names = "bus";
71		operating-points-v2 = <&bus_dmc_opp_table>;
72		samsung,data-clock-ratio = <4>;
73		#interconnect-cells = <0>;
74		status = "disabled";
75	};
76
77	bus_display: bus-display {
78		compatible = "samsung,exynos-bus";
79		clocks = <&clock CLK_ACLK160>;
80		clock-names = "bus";
81		operating-points-v2 = <&bus_display_opp_table>;
82		interconnects = <&bus_leftbus &bus_dmc>;
83		#interconnect-cells = <0>;
84		status = "disabled";
85
86		bus_display_opp_table: opp-table {
87			compatible = "operating-points-v2";
88
89			opp-160000000 {
90				opp-hz = /bits/ 64 <160000000>;
91			};
92			opp-200000000 {
93				opp-hz = /bits/ 64 <200000000>;
94			};
95		};
96	};
97
98	bus_fsys: bus-fsys {
99		compatible = "samsung,exynos-bus";
100		clocks = <&clock CLK_ACLK133>;
101		clock-names = "bus";
102		operating-points-v2 = <&bus_fsys_opp_table>;
103		status = "disabled";
104
105		bus_fsys_opp_table: opp-table {
106			compatible = "operating-points-v2";
107
108			opp-100000000 {
109				opp-hz = /bits/ 64 <100000000>;
110			};
111			opp-134000000 {
112				opp-hz = /bits/ 64 <134000000>;
113			};
114		};
115	};
116
117	bus_leftbus: bus-leftbus {
118		compatible = "samsung,exynos-bus";
119		clocks = <&clock CLK_DIV_GDL>;
120		clock-names = "bus";
121		operating-points-v2 = <&bus_leftbus_opp_table>;
122		interconnects = <&bus_dmc>;
123		#interconnect-cells = <0>;
124		status = "disabled";
125	};
126
127	bus_mfc: bus-mfc {
128		compatible = "samsung,exynos-bus";
129		clocks = <&clock CLK_SCLK_MFC>;
130		clock-names = "bus";
131		operating-points-v2 = <&bus_leftbus_opp_table>;
132		status = "disabled";
133	};
134
135	bus_peri: bus-peri {
136		compatible = "samsung,exynos-bus";
137		clocks = <&clock CLK_ACLK100>;
138		clock-names = "bus";
139		operating-points-v2 = <&bus_peri_opp_table>;
140		status = "disabled";
141
142		bus_peri_opp_table: opp-table {
143			compatible = "operating-points-v2";
144
145			opp-50000000 {
146				opp-hz = /bits/ 64 <50000000>;
147			};
148			opp-100000000 {
149				opp-hz = /bits/ 64 <100000000>;
150			};
151		};
152	};
153
154	bus_rightbus: bus-rightbus {
155		compatible = "samsung,exynos-bus";
156		clocks = <&clock CLK_DIV_GDR>;
157		clock-names = "bus";
158		operating-points-v2 = <&bus_leftbus_opp_table>;
159		status = "disabled";
160	};
161
162	cpus {
163		#address-cells = <1>;
164		#size-cells = <0>;
165
166		cpu-map {
167			cluster0 {
168				core0 {
169					cpu = <&cpu0>;
170				};
171				core1 {
172					cpu = <&cpu1>;
173				};
174				core2 {
175					cpu = <&cpu2>;
176				};
177				core3 {
178					cpu = <&cpu3>;
179				};
180			};
181		};
182
183		cpu0: cpu@a00 {
184			device_type = "cpu";
185			compatible = "arm,cortex-a9";
186			reg = <0xa00>;
187			clocks = <&clock CLK_ARM_CLK>;
188			clock-names = "cpu";
189			operating-points-v2 = <&cpu0_opp_table>;
190			#cooling-cells = <2>; /* min followed by max */
191		};
192
193		cpu1: cpu@a01 {
194			device_type = "cpu";
195			compatible = "arm,cortex-a9";
196			reg = <0xa01>;
197			clocks = <&clock CLK_ARM_CLK>;
198			clock-names = "cpu";
199			operating-points-v2 = <&cpu0_opp_table>;
200			#cooling-cells = <2>; /* min followed by max */
201		};
202
203		cpu2: cpu@a02 {
204			device_type = "cpu";
205			compatible = "arm,cortex-a9";
206			reg = <0xa02>;
207			clocks = <&clock CLK_ARM_CLK>;
208			clock-names = "cpu";
209			operating-points-v2 = <&cpu0_opp_table>;
210			#cooling-cells = <2>; /* min followed by max */
211		};
212
213		cpu3: cpu@a03 {
214			device_type = "cpu";
215			compatible = "arm,cortex-a9";
216			reg = <0xa03>;
217			clocks = <&clock CLK_ARM_CLK>;
218			clock-names = "cpu";
219			operating-points-v2 = <&cpu0_opp_table>;
220			#cooling-cells = <2>; /* min followed by max */
221		};
222	};
223
224	cpu0_opp_table: opp-table-0 {
225		compatible = "operating-points-v2";
226		opp-shared;
227
228		opp-200000000 {
229			opp-hz = /bits/ 64 <200000000>;
230			opp-microvolt = <900000>;
231			clock-latency-ns = <200000>;
232		};
233		opp-300000000 {
234			opp-hz = /bits/ 64 <300000000>;
235			opp-microvolt = <900000>;
236			clock-latency-ns = <200000>;
237		};
238		opp-400000000 {
239			opp-hz = /bits/ 64 <400000000>;
240			opp-microvolt = <925000>;
241			clock-latency-ns = <200000>;
242		};
243		opp-500000000 {
244			opp-hz = /bits/ 64 <500000000>;
245			opp-microvolt = <950000>;
246			clock-latency-ns = <200000>;
247		};
248		opp-600000000 {
249			opp-hz = /bits/ 64 <600000000>;
250			opp-microvolt = <975000>;
251			clock-latency-ns = <200000>;
252		};
253		opp-700000000 {
254			opp-hz = /bits/ 64 <700000000>;
255			opp-microvolt = <987500>;
256			clock-latency-ns = <200000>;
257		};
258		opp-800000000 {
259			opp-hz = /bits/ 64 <800000000>;
260			opp-microvolt = <1000000>;
261			clock-latency-ns = <200000>;
262			opp-suspend;
263		};
264		opp-900000000 {
265			opp-hz = /bits/ 64 <900000000>;
266			opp-microvolt = <1037500>;
267			clock-latency-ns = <200000>;
268		};
269		opp-1000000000 {
270			opp-hz = /bits/ 64 <1000000000>;
271			opp-microvolt = <1087500>;
272			clock-latency-ns = <200000>;
273		};
274		opp-1100000000 {
275			opp-hz = /bits/ 64 <1100000000>;
276			opp-microvolt = <1137500>;
277			clock-latency-ns = <200000>;
278		};
279		opp-1200000000 {
280			opp-hz = /bits/ 64 <1200000000>;
281			opp-microvolt = <1187500>;
282			clock-latency-ns = <200000>;
283		};
284		opp-1300000000 {
285			opp-hz = /bits/ 64 <1300000000>;
286			opp-microvolt = <1250000>;
287			clock-latency-ns = <200000>;
288		};
289		opp-1400000000 {
290			opp-hz = /bits/ 64 <1400000000>;
291			opp-microvolt = <1287500>;
292			clock-latency-ns = <200000>;
293		};
294		cpu0_opp_1500: opp-1500000000 {
295			opp-hz = /bits/ 64 <1500000000>;
296			opp-microvolt = <1350000>;
297			clock-latency-ns = <200000>;
298			turbo-mode;
299		};
300	};
301
302	bus_dmc_opp_table: opp-table-1 {
303		compatible = "operating-points-v2";
304
305		opp-100000000 {
306			opp-hz = /bits/ 64 <100000000>;
307			opp-microvolt = <900000>;
308		};
309		opp-134000000 {
310			opp-hz = /bits/ 64 <134000000>;
311			opp-microvolt = <900000>;
312		};
313		opp-160000000 {
314			opp-hz = /bits/ 64 <160000000>;
315			opp-microvolt = <900000>;
316		};
317		opp-267000000 {
318			opp-hz = /bits/ 64 <267000000>;
319			opp-microvolt = <950000>;
320		};
321		opp-400000000 {
322			opp-hz = /bits/ 64 <400000000>;
323			opp-microvolt = <1050000>;
324			opp-suspend;
325		};
326	};
327
328	bus_leftbus_opp_table: opp-table-2 {
329		compatible = "operating-points-v2";
330
331		opp-100000000 {
332			opp-hz = /bits/ 64 <100000000>;
333			opp-microvolt = <900000>;
334		};
335		opp-134000000 {
336			opp-hz = /bits/ 64 <134000000>;
337			opp-microvolt = <925000>;
338		};
339		opp-160000000 {
340			opp-hz = /bits/ 64 <160000000>;
341			opp-microvolt = <950000>;
342		};
343		opp-200000000 {
344			opp-hz = /bits/ 64 <200000000>;
345			opp-microvolt = <1000000>;
346			opp-suspend;
347		};
348	};
349
350	soc: soc {
351
352		pinctrl_0: pinctrl@11400000 {
353			compatible = "samsung,exynos4x12-pinctrl";
354			reg = <0x11400000 0x1000>;
355			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
356		};
357
358		pinctrl_1: pinctrl@11000000 {
359			compatible = "samsung,exynos4x12-pinctrl";
360			reg = <0x11000000 0x1000>;
361			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
362
363			wakup_eint: wakeup-interrupt-controller {
364				compatible = "samsung,exynos4210-wakeup-eint";
365				interrupt-parent = <&gic>;
366				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
367			};
368		};
369
370		pinctrl_2: pinctrl@3860000 {
371			compatible = "samsung,exynos4x12-pinctrl";
372			reg = <0x03860000 0x1000>;
373			interrupt-parent = <&combiner>;
374			interrupts = <10 0>;
375		};
376
377		pinctrl_3: pinctrl@106e0000 {
378			compatible = "samsung,exynos4x12-pinctrl";
379			reg = <0x106e0000 0x1000>;
380			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
381		};
382
383		sram@2020000 {
384			compatible = "mmio-sram";
385			reg = <0x02020000 0x40000>;
386			#address-cells = <1>;
387			#size-cells = <1>;
388			ranges = <0 0x02020000 0x40000>;
389
390			smp-sram@0 {
391				compatible = "samsung,exynos4210-sysram";
392				reg = <0x0 0x1000>;
393			};
394
395			smp-sram@2f000 {
396				compatible = "samsung,exynos4210-sysram-ns";
397				reg = <0x2f000 0x1000>;
398			};
399		};
400
401		pd_isp: power-domain@10023ca0 {
402			compatible = "samsung,exynos4210-pd";
403			reg = <0x10023ca0 0x20>;
404			#power-domain-cells = <0>;
405			label = "ISP";
406		};
407
408		l2c: cache-controller@10502000 {
409			compatible = "arm,pl310-cache";
410			reg = <0x10502000 0x1000>;
411			cache-unified;
412			cache-level = <2>;
413			prefetch-data = <1>;
414			prefetch-instr = <1>;
415			arm,tag-latency = <2 2 1>;
416			arm,data-latency = <3 2 1>;
417			arm,double-linefill = <1>;
418			arm,double-linefill-incr = <0>;
419			arm,double-linefill-wrap = <1>;
420			arm,prefetch-drop = <1>;
421			arm,prefetch-offset = <7>;
422		};
423
424		clock: clock-controller@10030000 {
425			compatible = "samsung,exynos4412-clock";
426			reg = <0x10030000 0x18000>;
427			#clock-cells = <1>;
428		};
429
430		isp_clock: clock-controller@10048000 {
431			compatible = "samsung,exynos4412-isp-clock";
432			reg = <0x10048000 0x1000>;
433			#clock-cells = <1>;
434			power-domains = <&pd_isp>;
435			clocks = <&clock CLK_ACLK200>,
436				 <&clock CLK_ACLK400_MCUISP>;
437			clock-names = "aclk200", "aclk400_mcuisp";
438		};
439
440		timer@10050000 {
441			compatible = "samsung,exynos4412-mct";
442			reg = <0x10050000 0x800>;
443			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
444			clock-names = "fin_pll", "mct";
445			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
446					      <&combiner 12 5>,
447					      <&combiner 12 6>,
448					      <&combiner 12 7>,
449					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
450		};
451
452		watchdog: watchdog@10060000 {
453			compatible = "samsung,exynos5250-wdt";
454			reg = <0x10060000 0x100>;
455			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
456			clocks = <&clock CLK_WDT>;
457			clock-names = "watchdog";
458			samsung,syscon-phandle = <&pmu_system_controller>;
459		};
460
461		adc: adc@126c0000 {
462			compatible = "samsung,exynos4212-adc";
463			reg = <0x126c0000 0x100>;
464			interrupt-parent = <&combiner>;
465			interrupts = <10 3>;
466			clocks = <&clock CLK_TSADC>;
467			clock-names = "adc";
468			#io-channel-cells = <1>;
469			samsung,syscon-phandle = <&pmu_system_controller>;
470			status = "disabled";
471		};
472
473		g2d: g2d@10800000 {
474			compatible = "samsung,exynos4212-g2d";
475			reg = <0x10800000 0x1000>;
476			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
477			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
478			clock-names = "sclk_fimg2d", "fimg2d";
479			iommus = <&sysmmu_g2d>;
480		};
481
482		mshc_0: mmc@12550000 {
483			compatible = "samsung,exynos4412-dw-mshc";
484			reg = <0x12550000 0x1000>;
485			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
486			#address-cells = <1>;
487			#size-cells = <0>;
488			fifo-depth = <0x80>;
489			clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
490			clock-names = "biu", "ciu";
491			status = "disabled";
492		};
493
494		sysmmu_g2d: sysmmu@10a40000 {
495			compatible = "samsung,exynos-sysmmu";
496			reg = <0x10a40000 0x1000>;
497			interrupt-parent = <&combiner>;
498			interrupts = <4 7>;
499			clock-names = "sysmmu", "master";
500			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
501			#iommu-cells = <0>;
502		};
503
504		sysmmu_fimc_isp: sysmmu@12260000 {
505			compatible = "samsung,exynos-sysmmu";
506			reg = <0x12260000 0x1000>;
507			interrupt-parent = <&combiner>;
508			interrupts = <16 2>;
509			power-domains = <&pd_isp>;
510			clock-names = "sysmmu";
511			clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
512			#iommu-cells = <0>;
513		};
514
515		sysmmu_fimc_drc: sysmmu@12270000 {
516			compatible = "samsung,exynos-sysmmu";
517			reg = <0x12270000 0x1000>;
518			interrupt-parent = <&combiner>;
519			interrupts = <16 3>;
520			power-domains = <&pd_isp>;
521			clock-names = "sysmmu";
522			clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
523			#iommu-cells = <0>;
524		};
525
526		sysmmu_fimc_fd: sysmmu@122a0000 {
527			compatible = "samsung,exynos-sysmmu";
528			reg = <0x122a0000 0x1000>;
529			interrupt-parent = <&combiner>;
530			interrupts = <16 4>;
531			power-domains = <&pd_isp>;
532			clock-names = "sysmmu";
533			clocks = <&isp_clock CLK_ISP_SMMU_FD>;
534			#iommu-cells = <0>;
535		};
536
537		sysmmu_fimc_mcuctl: sysmmu@122b0000 {
538			compatible = "samsung,exynos-sysmmu";
539			reg = <0x122b0000 0x1000>;
540			interrupt-parent = <&combiner>;
541			interrupts = <16 5>;
542			power-domains = <&pd_isp>;
543			clock-names = "sysmmu";
544			clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
545			#iommu-cells = <0>;
546		};
547
548		sysmmu_fimc_lite0: sysmmu@123b0000 {
549			compatible = "samsung,exynos-sysmmu";
550			reg = <0x123b0000 0x1000>;
551			interrupt-parent = <&combiner>;
552			interrupts = <16 0>;
553			power-domains = <&pd_isp>;
554			clock-names = "sysmmu", "master";
555			clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
556				 <&isp_clock CLK_ISP_FIMC_LITE0>;
557			#iommu-cells = <0>;
558		};
559
560		sysmmu_fimc_lite1: sysmmu@123c0000 {
561			compatible = "samsung,exynos-sysmmu";
562			reg = <0x123c0000 0x1000>;
563			interrupt-parent = <&combiner>;
564			interrupts = <16 1>;
565			power-domains = <&pd_isp>;
566			clock-names = "sysmmu", "master";
567			clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
568				 <&isp_clock CLK_ISP_FIMC_LITE1>;
569			#iommu-cells = <0>;
570		};
571	};
572};
573
574&combiner {
575	samsung,combiner-nr = <20>;
576	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
577		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
578		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
579		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
580		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
581		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
582		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
583		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
584		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
585		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
586		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
587		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
588		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
589		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
590		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
591		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
592		     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
593		     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
594		     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
595		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
596};
597
598&camera {
599	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
600		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
601	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
602
603	/* fimc_[0-3] are configured outside, under phandles */
604	fimc_lite_0: fimc-lite@12390000 {
605		compatible = "samsung,exynos4212-fimc-lite";
606		reg = <0x12390000 0x1000>;
607		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
608		power-domains = <&pd_isp>;
609		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
610		clock-names = "flite";
611		iommus = <&sysmmu_fimc_lite0>;
612		status = "disabled";
613	};
614
615	fimc_lite_1: fimc-lite@123a0000 {
616		compatible = "samsung,exynos4212-fimc-lite";
617		reg = <0x123a0000 0x1000>;
618		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
619		power-domains = <&pd_isp>;
620		clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
621		clock-names = "flite";
622		iommus = <&sysmmu_fimc_lite1>;
623		status = "disabled";
624	};
625
626	fimc_is: fimc-is@12000000 {
627		compatible = "samsung,exynos4212-fimc-is";
628		reg = <0x12000000 0x260000>;
629		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
630			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
631		power-domains = <&pd_isp>;
632		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
633			 <&isp_clock CLK_ISP_FIMC_LITE1>,
634			 <&isp_clock CLK_ISP_PPMUISPX>,
635			 <&isp_clock CLK_ISP_PPMUISPMX>,
636			 <&isp_clock CLK_ISP_FIMC_ISP>,
637			 <&isp_clock CLK_ISP_FIMC_DRC>,
638			 <&isp_clock CLK_ISP_FIMC_FD>,
639			 <&isp_clock CLK_ISP_MCUISP>,
640			 <&isp_clock CLK_ISP_GICISP>,
641			 <&isp_clock CLK_ISP_MCUCTL_ISP>,
642			 <&isp_clock CLK_ISP_PWM_ISP>,
643			 <&isp_clock CLK_ISP_DIV_ISP0>,
644			 <&isp_clock CLK_ISP_DIV_ISP1>,
645			 <&isp_clock CLK_ISP_DIV_MCUISP0>,
646			 <&isp_clock CLK_ISP_DIV_MCUISP1>,
647			 <&clock CLK_MOUT_MPLL_USER_T>,
648			 <&clock CLK_ACLK200>,
649			 <&clock CLK_ACLK400_MCUISP>,
650			 <&clock CLK_DIV_ACLK200>,
651			 <&clock CLK_DIV_ACLK400_MCUISP>,
652			 <&clock CLK_UART_ISP_SCLK>;
653		clock-names = "lite0", "lite1", "ppmuispx",
654			      "ppmuispmx", "isp",
655			      "drc", "fd", "mcuisp",
656			      "gicisp", "mcuctl_isp", "pwm_isp",
657			      "ispdiv0", "ispdiv1", "mcuispdiv0",
658			      "mcuispdiv1", "mpll", "aclk200",
659			      "aclk400mcuisp", "div_aclk200",
660			      "div_aclk400mcuisp", "uart";
661		iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
662			 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
663		iommu-names = "isp", "drc", "fd", "mcuctl";
664		#address-cells = <1>;
665		#size-cells = <1>;
666		ranges;
667		status = "disabled";
668
669		pmu@10020000 {
670			reg = <0x10020000 0x3000>;
671		};
672
673		i2c1_isp: i2c-isp@12140000 {
674			compatible = "samsung,exynos4212-i2c-isp";
675			reg = <0x12140000 0x100>;
676			clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
677			clock-names = "i2c_isp";
678			#address-cells = <1>;
679			#size-cells = <0>;
680		};
681	};
682};
683
684&exynos_usbphy {
685	compatible = "samsung,exynos4x12-usb2-phy";
686	samsung,sysreg-phandle = <&sys_reg>;
687};
688
689&fimc_0 {
690	compatible = "samsung,exynos4212-fimc";
691	samsung,pix-limits = <4224 8192 1920 4224>;
692	samsung,mainscaler-ext;
693	samsung,isp-wb;
694	samsung,cam-if;
695};
696
697&fimc_1 {
698	compatible = "samsung,exynos4212-fimc";
699	samsung,pix-limits = <4224 8192 1920 4224>;
700	samsung,mainscaler-ext;
701	samsung,isp-wb;
702	samsung,cam-if;
703};
704
705&fimc_2 {
706	compatible = "samsung,exynos4212-fimc";
707	samsung,pix-limits = <4224 8192 1920 4224>;
708	samsung,mainscaler-ext;
709	samsung,isp-wb;
710	samsung,lcd-wb;
711	samsung,cam-if;
712};
713
714&fimc_3 {
715	compatible = "samsung,exynos4212-fimc";
716	samsung,pix-limits = <1920 8192 1366 1920>;
717	samsung,rotators = <0>;
718	samsung,mainscaler-ext;
719	samsung,isp-wb;
720	samsung,lcd-wb;
721};
722
723&gic {
724	cpu-offset = <0x4000>;
725};
726
727&gpu {
728	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
729		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
730		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
731		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
732		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
733		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
734		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
735		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
736		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
737		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
738		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
739	interrupt-names = "gp",
740			  "gpmmu",
741			  "pp0",
742			  "ppmmu0",
743			  "pp1",
744			  "ppmmu1",
745			  "pp2",
746			  "ppmmu2",
747			  "pp3",
748			  "ppmmu3",
749			  "pmu";
750	operating-points-v2 = <&gpu_opp_table>;
751
752	gpu_opp_table: opp-table {
753		compatible = "operating-points-v2";
754
755		opp-160000000 {
756			opp-hz = /bits/ 64 <160000000>;
757			opp-microvolt = <875000>;
758		};
759		opp-267000000 {
760			opp-hz = /bits/ 64 <267000000>;
761			opp-microvolt = <900000>;
762		};
763		opp-350000000 {
764			opp-hz = /bits/ 64 <350000000>;
765			opp-microvolt = <950000>;
766		};
767		opp-440000000 {
768			opp-hz = /bits/ 64 <440000000>;
769			opp-microvolt = <1025000>;
770		};
771	};
772};
773
774&hdmi {
775	compatible = "samsung,exynos4212-hdmi";
776};
777
778&jpeg_codec {
779	compatible = "samsung,exynos4212-jpeg";
780};
781
782&rotator {
783	compatible = "samsung,exynos4212-rotator";
784};
785
786&mixer {
787	compatible = "samsung,exynos4212-mixer";
788	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
789	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
790		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
791	interconnects = <&bus_display &bus_dmc>;
792};
793
794&pmu {
795	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
796	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
797	status = "okay";
798};
799
800&pmu_system_controller {
801	compatible = "samsung,exynos4412-pmu", "syscon";
802	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
803			"clkout4", "clkout8", "clkout9";
804	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
805		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
806		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
807	#clock-cells = <1>;
808};
809
810&tmu {
811	compatible = "samsung,exynos4412-tmu";
812	interrupt-parent = <&combiner>;
813	interrupts = <2 4>;
814	reg = <0x100c0000 0x100>;
815	clocks = <&clock CLK_TMU_APBIF>;
816	clock-names = "tmu_apbif";
817	status = "disabled";
818};
819
820#include "exynos4412-pinctrl.dtsi"
821