1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright (c) 2016 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
5 */
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/leds/common.h>
10#include <dt-bindings/sound/fsl-imx-audmux.h>
11#include "imx6dl.dtsi"
12
13/ {
14	model = "Altesco I6P Board";
15	compatible = "alt,alti6p", "fsl,imx6dl";
16
17	chosen {
18		stdout-path = &uart4;
19	};
20
21	clock_ksz8081: clock-ksz8081 {
22		compatible = "fixed-clock";
23		#clock-cells = <0>;
24		clock-frequency = <50000000>;
25	};
26
27	i2c2-mux {
28		compatible = "i2c-mux";
29		i2c-parent = <&i2c2>;
30		mux-controls = <&i2c_mux>;
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		i2c@1 {
35			reg = <1>;
36			#address-cells = <1>;
37			#size-cells = <0>;
38		};
39
40		i2c@2 {
41			reg = <2>;
42			#address-cells = <1>;
43			#size-cells = <0>;
44		};
45	};
46
47	i2c4-mux {
48		compatible = "i2c-mux";
49		i2c-parent = <&i2c4>;
50		mux-controls = <&i2c_mux>;
51		#address-cells = <1>;
52		#size-cells = <0>;
53
54		i2c@1 {
55			reg = <1>;
56			#address-cells = <1>;
57			#size-cells = <0>;
58		};
59
60		i2c@2 {
61			reg = <2>;
62			#address-cells = <1>;
63			#size-cells = <0>;
64		};
65	};
66
67	leds {
68		compatible = "gpio-leds";
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_leds>;
71
72		led-debug0 {
73			function = LED_FUNCTION_STATUS;
74			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
75			linux,default-trigger = "heartbeat";
76		};
77
78		led-debug1 {
79			function = LED_FUNCTION_SD;
80			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
81			linux,default-trigger = "disk-activity";
82		};
83	};
84
85	i2c_mux: mux-controller {
86		compatible = "gpio-mux";
87		#mux-control-cells = <0>;
88		pinctrl-names = "default";
89		pinctrl-0 = <&pinctrl_i2cmux>;
90
91		mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>,
92			    <&gpio5 11 GPIO_ACTIVE_HIGH>;
93	};
94
95	reg_1v8: regulator-1v8 {
96		compatible = "regulator-fixed";
97		regulator-name = "1v8";
98		regulator-min-microvolt = <1800000>;
99		regulator-max-microvolt = <1800000>;
100	};
101
102	reg_3v3: regulator-3v3 {
103		compatible = "regulator-fixed";
104		regulator-name = "3v3";
105		regulator-min-microvolt = <3300000>;
106		regulator-max-microvolt = <3300000>;
107	};
108
109	reg_5v0: regulator-5v0 {
110		compatible = "regulator-fixed";
111		regulator-name = "5v0";
112		regulator-min-microvolt = <5000000>;
113		regulator-max-microvolt = <5000000>;
114	};
115
116	reg_h1_vbus: regulator-h1-vbus {
117		compatible = "regulator-fixed";
118		regulator-name = "h1-vbus";
119		regulator-min-microvolt = <5000000>;
120		regulator-max-microvolt = <5000000>;
121		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
122		enable-active-high;
123	};
124
125	reg_otg_vbus: regulator-otg-vbus {
126		compatible = "regulator-fixed";
127		regulator-name = "otg-vbus";
128		regulator-min-microvolt = <5000000>;
129		regulator-max-microvolt = <5000000>;
130		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
131		enable-active-high;
132	};
133
134	sound {
135		compatible = "simple-audio-card";
136		simple-audio-card,name = "prti6q-sgtl5000";
137		simple-audio-card,format = "i2s";
138		simple-audio-card,widgets =
139			"Microphone", "Microphone Jack",
140			"Line", "Line In Jack",
141			"Headphone", "Headphone Jack",
142			"Speaker", "External Speaker";
143		simple-audio-card,routing =
144			"MIC_IN", "Microphone Jack",
145			"LINE_IN", "Line In Jack",
146			"Headphone Jack", "HP_OUT",
147			"External Speaker", "LINE_OUT";
148
149		simple-audio-card,cpu {
150			sound-dai = <&ssi1>;
151			system-clock-frequency = <0>;
152		};
153
154		simple-audio-card,codec {
155			sound-dai = <&sgtl5000>;
156			bitclock-master;
157			frame-master;
158		};
159	};
160};
161
162&audmux {
163	pinctrl-names = "default";
164	pinctrl-0 = <&pinctrl_audmux>;
165	status = "okay";
166
167	mux-ssi1 {
168		fsl,audmux-port = <0>;
169		fsl,port-config = <
170			IMX_AUDMUX_V2_PTCR_SYN		0
171			IMX_AUDMUX_V2_PTCR_TFSEL(2)	0
172			IMX_AUDMUX_V2_PTCR_TCSEL(2)	0
173			IMX_AUDMUX_V2_PTCR_TFSDIR	0
174			IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
175		>;
176	};
177
178	mux-pins3 {
179		fsl,audmux-port = <2>;
180		fsl,port-config = <
181			IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
182			0		       IMX_AUDMUX_V2_PDCR_TXRXEN
183		>;
184	};
185};
186
187&can1 {
188	pinctrl-names = "default";
189	pinctrl-0 = <&pinctrl_can1>;
190	xceiver-supply = <&reg_5v0>;
191	status = "okay";
192};
193
194&ecspi1 {
195	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_ecspi1>;
198	status = "okay";
199
200	flash@0 {
201		compatible = "jedec,spi-nor";
202		reg = <0>;
203		spi-max-frequency = <20000000>;
204	};
205};
206
207&fec {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_enet>;
210	phy-mode = "rmii";
211	clocks = <&clks IMX6QDL_CLK_ENET>,
212		 <&clks IMX6QDL_CLK_ENET>,
213		 <&clock_ksz8081>;
214	clock-names = "ipg", "ahb", "ptp";
215	status = "okay";
216
217	mdio {
218		#address-cells = <1>;
219		#size-cells = <0>;
220
221		/* Microchip KSZ8081RNA PHY */
222		rgmii_phy: ethernet-phy@0 {
223			reg = <0>;
224			interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
225			reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
226			reset-assert-us = <10000>;
227			reset-deassert-us = <300>;
228		};
229	};
230};
231
232&gpio1 {
233	gpio-line-names =
234		"", "SD1_CD", "", "USB_H1_OC", "", "", "", "",
235		"DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
236		"", "", "", "", "", "", "", "",
237		"", "", "", "", "", "", "", "";
238};
239
240&gpio3 {
241	gpio-line-names =
242		"", "", "", "", "", "", "", "",
243		"", "", "", "", "", "", "", "",
244		"", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "",
245		"", "", "", "", "", "", "", "";
246};
247
248&gpio4 {
249	gpio-line-names =
250		"", "", "", "", "", "", "", "",
251		"", "", "", "", "", "", "", "",
252		"", "", "", "", "", "", "", "",
253		"", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", "";
254};
255
256&gpio5 {
257	gpio-line-names =
258		"", "", "", "", "", "", "", "",
259		"", "", "I2C_EN13", "I2C_EN24", "", "", "", "",
260		"", "", "", "", "", "AUDIO_RESET", "", "",
261		"", "", "", "", "", "", "", "";
262};
263
264&hdmi {
265	pinctrl-names = "default";
266	pinctrl-0 = <&pinctrl_hdmi>;
267	ddc-i2c-bus = <&i2c1>;
268	status = "okay";
269};
270
271/* DDC */
272&i2c1 {
273	clock-frequency = <100000>;
274	pinctrl-names = "default";
275	pinctrl-0 = <&pinctrl_i2c1>;
276	status = "okay";
277
278	sgtl5000: audio-codec@a {
279		compatible = "fsl,sgtl5000";
280		reg = <0xa>;
281		#sound-dai-cells = <0>;
282		clocks = <&clks 201>;
283		VDDA-supply = <&reg_3v3>;
284		VDDIO-supply = <&reg_3v3>;
285		VDDD-supply = <&reg_1v8>;
286	};
287
288	/* additional i2c devices are added automatically by the boot loader */
289};
290
291&i2c2 {
292	clock-frequency = <50000>;
293	pinctrl-names = "default";
294	pinctrl-0 = <&pinctrl_i2c2>;
295	status = "okay";
296
297	/* external interface, device are configured from user space */
298};
299
300&i2c3 {
301	clock-frequency = <100000>;
302	pinctrl-names = "default";
303	pinctrl-0 = <&pinctrl_i2c3>;
304	status = "okay";
305
306	rtc@51 {
307		compatible = "nxp,pcf8563";
308		reg = <0x51>;
309	};
310
311	temperature-sensor@70 {
312		compatible = "ti,tmp103";
313		reg = <0x70>;
314	};
315};
316
317&i2c4 {
318	clock-frequency = <50000>;
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_i2c4>;
321	status = "okay";
322};
323
324&pwm1 {
325	pinctrl-names = "default";
326	pinctrl-0 = <&pinctrl_pwm1>;
327	status = "okay";
328};
329
330&ssi1 {
331	#sound-dai-cells = <0>;
332	fsl,mode = "ac97-slave";
333	status = "okay";
334};
335
336&uart2 {
337	pinctrl-names = "default";
338	pinctrl-0 = <&pinctrl_uart2>;
339	status = "okay";
340};
341
342&uart4 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_uart4>;
345	status = "okay";
346};
347
348&uart5 {
349	pinctrl-names = "default";
350	pinctrl-0 = <&pinctrl_uart5>;
351	status = "okay";
352};
353
354&usbh1 {
355	vbus-supply = <&reg_h1_vbus>;
356	pinctrl-names = "default";
357	pinctrl-0 = <&pinctrl_usbh1>;
358	phy_type = "utmi";
359	dr_mode = "host";
360	status = "okay";
361};
362
363&usbotg {
364	vbus-supply = <&reg_otg_vbus>;
365	pinctrl-names = "default";
366	pinctrl-0 = <&pinctrl_usbotg>;
367	phy_type = "utmi";
368	dr_mode = "host";
369	status = "okay";
370};
371
372&usdhc1 {
373	pinctrl-names = "default";
374	pinctrl-0 = <&pinctrl_usdhc1>;
375	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
376	no-1-8-v;
377	disable-wp;
378	cap-sd-highspeed;
379	no-mmc;
380	no-sdio;
381	status = "okay";
382};
383
384&usdhc3 {
385	pinctrl-names = "default";
386	pinctrl-0 = <&pinctrl_usdhc3>;
387	bus-width = <8>;
388	no-1-8-v;
389	non-removable;
390	no-sd;
391	no-sdio;
392	status = "okay";
393};
394
395&iomuxc {
396	pinctrl_audmux: audmuxgrp {
397		fsl,pins = <
398			MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1			0x030b0
399			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD			0x130b0
400			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC			0x130b0
401			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD			0x110b0
402			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS			0x130b0
403		>;
404	};
405
406	pinctrl_can1: can1grp {
407		fsl,pins = <
408			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX		0x1b000
409			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX		0x3008
410		>;
411	};
412
413	pinctrl_ecspi1: ecspi1grp {
414		fsl,pins = <
415			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x1b000
416			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0x3008
417			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0x3008
418			/* CS */
419			MX6QDL_PAD_EIM_D19__GPIO3_IO19			0x3008
420		>;
421	};
422
423	pinctrl_enet: enetgrp {
424		fsl,pins = <
425			/* MX6QDL_ENET_PINGRP4 */
426			MX6QDL_PAD_ENET_MDC__ENET_MDC			0x1b0b0
427			MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x1b0b0
428			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x1b0b0
429			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x1b0b0
430			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER		0x1b0b0
431			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x1b0b0
432			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x1b0b0
433			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x1b0b0
434			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x1b0b0
435
436			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0
437			/* Phy reset */
438			MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26		0x1b0b0
439			/* nINTRP */
440			MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30		0x1b0b0
441		>;
442	};
443
444	pinctrl_hdmi: hdmigrp {
445		fsl,pins = <
446			/* NOTE: DDC is done via I2C2, so DON'T configure DDC
447			 * pins for HDMI!
448			 */
449			MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE		0x1f8b0
450		>;
451	};
452
453	pinctrl_i2c1: i2c1grp {
454		fsl,pins = <
455			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA			0x4001f8b1
456			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL			0x4001f8b1
457		>;
458	};
459
460	pinctrl_i2c2: i2c2grp {
461		fsl,pins = <
462			MX6QDL_PAD_KEY_COL3__I2C2_SCL			0x4001b8b1
463			MX6QDL_PAD_KEY_ROW3__I2C2_SDA			0x4001b8b1
464		>;
465	};
466
467	pinctrl_i2c3: i2c3grp {
468		fsl,pins = <
469			MX6QDL_PAD_GPIO_5__I2C3_SCL			0x4001b8b1
470			MX6QDL_PAD_GPIO_6__I2C3_SDA			0x4001b8b1
471		>;
472	};
473
474	pinctrl_i2c4: i2c4grp {
475		fsl,pins = <
476			MX6QDL_PAD_NANDF_CS3__I2C4_SDA			0x4001f8b1
477			MX6QDL_PAD_NANDF_WP_B__I2C4_SCL			0x4001f8b1
478		>;
479	};
480
481	pinctrl_i2cmux: i2cmuxgrp {
482		fsl,pins = <
483			MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10		0x1b0b0
484			MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11		0x1b0b0
485		>;
486	};
487
488	pinctrl_leds: ledsgrp {
489		fsl,pins = <
490			MX6QDL_PAD_GPIO_8__GPIO1_IO08			0x1b0b0
491			MX6QDL_PAD_GPIO_9__GPIO1_IO09			0x1b0b0
492		>;
493	};
494
495	pinctrl_pwm1: pwm1grp {
496		fsl,pins = <
497			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT			0x8
498		>;
499	};
500
501	pinctrl_uart2: uart2grp {
502		fsl,pins = <
503			MX6QDL_PAD_EIM_D26__UART2_TX_DATA		0x1b0b1
504			MX6QDL_PAD_EIM_D27__UART2_RX_DATA		0x1b0b1
505		>;
506	};
507
508	pinctrl_uart4: uart4grp {
509		fsl,pins = <
510			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA		0x1b0b1
511			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA		0x1b0b1
512		>;
513	};
514
515	pinctrl_uart5: uart5grp {
516		fsl,pins = <
517			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA		0x1b0b1
518			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA		0x1b0b1
519		>;
520	};
521
522	pinctrl_usbh1: usbh1grp {
523		fsl,pins = <
524			MX6QDL_PAD_GPIO_3__USB_H1_OC			0x1B058
525			MX6QDL_PAD_GPIO_0__GPIO1_IO00			0x1B058
526
527		>;
528	};
529
530	pinctrl_usbotg: usbotggrp {
531		fsl,pins = <
532			MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x1b0b0
533			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
534		>;
535	};
536
537	pinctrl_usdhc1: usdhc1grp {
538		fsl,pins = <
539			MX6QDL_PAD_SD1_CMD__SD1_CMD			0x170f9
540			MX6QDL_PAD_SD1_CLK__SD1_CLK			0x100f9
541			MX6QDL_PAD_SD1_DAT0__SD1_DATA0			0x170f9
542			MX6QDL_PAD_SD1_DAT1__SD1_DATA1			0x170f9
543			MX6QDL_PAD_SD1_DAT2__SD1_DATA2			0x170f9
544			MX6QDL_PAD_SD1_DAT3__SD1_DATA3			0x170f9
545			MX6QDL_PAD_GPIO_1__GPIO1_IO01			0x1b0b0
546		>;
547	};
548
549	pinctrl_usdhc3: usdhc3grp {
550		fsl,pins = <
551			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17099
552			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10099
553			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17099
554			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17099
555			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17099
556			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17099
557			MX6QDL_PAD_SD3_DAT4__SD3_DATA4			0x17099
558			MX6QDL_PAD_SD3_DAT5__SD3_DATA5			0x17099
559			MX6QDL_PAD_SD3_DAT6__SD3_DATA6			0x17099
560			MX6QDL_PAD_SD3_DAT7__SD3_DATA7			0x17099
561			MX6QDL_PAD_SD3_RST__SD3_RESET			0x1b0b1
562		>;
563	};
564};
565