1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2013 Sascha Hauer, Pengutronix 4 * 5 * Copyright 2013-2021 TQ-Systems GmbH 6 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 7 */ 8 9#include <dt-bindings/clock/imx6qdl-clock.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/sound/fsl-imx-audmux.h> 13 14/ { 15 aliases { 16 mmc0 = &usdhc3; 17 mmc1 = &usdhc2; 18 /delete-property/ mmc2; 19 /delete-property/ mmc3; 20 rtc0 = &rtc0; 21 }; 22 23 chosen { 24 stdout-path = &uart2; 25 }; 26 27 beeper: gpio-beeper { 28 compatible = "gpio-beeper"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_gpiobeeper>; 31 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 32 }; 33 34 gpio_buttons: gpio-buttons { 35 compatible = "gpio-keys"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&pinctrl_gpiobuttons>; 38 39 button1 { 40 label = "s6"; 41 linux,code = <KEY_F6>; 42 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 43 wakeup-source; 44 }; 45 46 button2 { 47 label = "s7"; 48 linux,code = <KEY_F7>; 49 gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 50 wakeup-source; 51 }; 52 53 button3 { 54 label = "s8"; 55 linux,code = <KEY_F8>; 56 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 57 wakeup-source; 58 }; 59 }; 60 61 gpio-leds { 62 compatible = "gpio-leds"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_gpioled>; 65 66 led1 { 67 label = "led1"; 68 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 69 linux,default-trigger = "default-on"; 70 }; 71 72 led2 { 73 label = "led2"; 74 gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; 75 linux,default-trigger = "heartbeat"; 76 }; 77 }; 78 79 reg_mba6_3p3v: regulator-mba6-3p3v { 80 compatible = "regulator-fixed"; 81 regulator-name = "supply-mba6-3p3v"; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 regulator-always-on; 85 }; 86 87 reg_pcie: regulator-pcie { 88 compatible = "regulator-fixed"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_regpcie>; 91 regulator-name = "supply-pcie"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 /* PCIE.PWR_EN */ 95 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 regulator-always-on; 98 vin-supply = <®_mba6_3p3v>; 99 }; 100 101 reg_vcc3v3_audio: regulator-vcc3v3-audio { 102 compatible = "regulator-fixed"; 103 regulator-name = "vcc3v3-audio"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 vin-supply = <®_mba6_3p3v>; 107 }; 108 109 sound { 110 compatible = "fsl,imx-audio-tlv320aic32x4"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_audmux>; 113 model = "imx-audio-tlv320aic32x4"; 114 ssi-controller = <&ssi1>; 115 audio-codec = <&tlv320aic32x4>; 116 audio-asrc = <&asrc>; 117 audio-routing = 118 "IN3_L", "Mic Jack", 119 "Mic Jack", "Mic Bias", 120 "IN1_L", "Line In Jack", 121 "IN1_R", "Line In Jack", 122 "Line Out Jack", "LOL", 123 "Line Out Jack", "LOR"; 124 mux-int-port = <1>; 125 mux-ext-port = <3>; 126 }; 127}; 128 129&audmux { 130 status = "okay"; 131 132 ssi0 { 133 fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>; 134 fsl,port-config = < 135 (IMX_AUDMUX_V2_PTCR_SYN | 136 IMX_AUDMUX_V2_PTCR_TFSDIR | 137 IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | 138 IMX_AUDMUX_V2_PTCR_TCLKDIR | 139 IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) 140 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) 141 >; 142 }; 143 144 aud3 { 145 fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>; 146 fsl,port-config = < 147 IMX_AUDMUX_V2_PTCR_SYN 148 IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) 149 >; 150 }; 151}; 152 153&can1 { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_can1>; 156 status = "okay"; 157}; 158 159&can2 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_can2>; 162 status = "okay"; 163}; 164 165&ecspi1 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; 168 cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; 169}; 170 171&fec { 172 phy-mode = "rgmii-id"; 173 phy-handle = <ðphy>; 174 mac-address = [00 00 00 00 00 00]; 175 status = "okay"; 176 177 mdio { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 ethphy: ethernet-phy@3 { 182 compatible = "ethernet-phy-ieee802.3-c22"; 183 reg = <3>; 184 interrupt-parent = <&gpio1>; 185 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 186 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 187 reset-assert-us = <1000>; 188 reset-deassert-us = <100000>; 189 micrel,force-master; 190 max-speed = <1000>; 191 }; 192 }; 193}; 194 195&i2c1 { 196 tlv320aic32x4: audio-codec@18 { 197 compatible = "ti,tlv320aic32x4"; 198 reg = <0x18>; 199 clocks = <&clks IMX6QDL_CLK_CKO>; 200 clock-names = "mclk"; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_codec>; 203 ldoin-supply = <®_vcc3v3_audio>; 204 iov-supply = <®_mba6_3p3v>; 205 }; 206}; 207 208&pcie { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_pcie>; 211 reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; 212 status = "okay"; 213}; 214 215&pwm1 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_pwm1>; 218 status = "okay"; 219}; 220 221&pwm3 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_pwm3>; 224 status = "okay"; 225}; 226 227&pwm4 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_pwm4>; 230 status = "okay"; 231}; 232 233&snvs_poweroff { 234 status = "okay"; 235}; 236 237&ssi1 { 238 status = "okay"; 239}; 240 241&uart2 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_uart2>; 244 status = "okay"; 245}; 246 247&uart3 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_uart3>; 250 uart-has-rtscts; 251 status = "okay"; 252}; 253 254&uart4 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_uart4>; 257 uart-has-rtscts; 258 linux,rs485-enabled-at-boot-time; 259 rs485-rts-active-low; 260 rs485-rx-during-tx; 261 status = "okay"; 262}; 263 264&uart5 { 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_uart5>; 267 uart-has-rtscts; 268 status = "okay"; 269}; 270 271&usbh1 { 272 disable-over-current; 273 status = "okay"; 274}; 275 276&usbotg { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_usbotg>; 279 power-active-high; 280 over-current-active-low; 281 srp-disable; 282 hnp-disable; 283 adp-disable; 284 dr_mode = "otg"; 285 status = "okay"; 286}; 287 288/* SD card slot */ 289&usdhc2 { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_usdhc2>; 292 vmmc-supply = <®_mba6_3p3v>; 293 bus-width = <4>; 294 no-1-8-v; 295 no-mmc; 296 no-sdio; 297 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 298 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 299 status = "okay"; 300}; 301 302&wdog1 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_wdog1>; 305 /* does not work on unmodified starter kit */ 306 /* fsl,ext-reset-output; */ 307 status = "okay"; 308}; 309 310&iomuxc { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_hog>; 313 314 pinctrl_audmux: audmuxgrp { 315 fsl,pins = < 316 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 317 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 318 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 319 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 320 >; 321 }; 322 323 pinctrl_can1: can1grp { 324 fsl,pins = < 325 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 326 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 327 >; 328 }; 329 330 pinctrl_can2: can2grp { 331 fsl,pins = < 332 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 333 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 334 >; 335 }; 336 337 pinctrl_codec: codecgrp { 338 fsl,pins = < 339 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ 340 >; 341 }; 342 343 pinctrl_ecspi1_mba6: ecspimba6grp { 344 fsl,pins = < 345 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ 346 >; 347 }; 348 349 pinctrl_enet: enetgrp { 350 fsl,pins = < 351 /* FEC phy IRQ */ 352 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 353 /* FEC phy reset */ 354 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 355 /* DSE = 100, 100k up, SPEED = MED */ 356 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 357 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 358 /* DSE = 111, pull 100k up */ 359 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 360 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 361 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 362 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 363 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 364 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 365 /* DSE = 111, pull external */ 366 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 367 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 368 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 369 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 370 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 371 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 372 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ 373 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 374 >; 375 }; 376 377 pinctrl_gpiobeeper: gpiobeepergrp { 378 fsl,pins = < 379 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 380 >; 381 }; 382 383 pinctrl_gpiobuttons: gpiobuttongrp { 384 fsl,pins = < 385 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 386 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 387 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 388 >; 389 }; 390 391 pinctrl_gpioled: gpioledgrp { 392 fsl,pins = < 393 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ 394 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ 395 >; 396 }; 397 398 pinctrl_hog: hoggrp { 399 fsl,pins = < 400 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 401 402 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 403 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 404 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 405 406 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 407 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 408 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 409 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 410 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 411 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 412 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 413 414 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 415 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 416 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 417 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 418 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 419 420 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 421 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 422 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 423 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 424 425 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 426 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 427 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 428 429 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 430 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 431 >; 432 }; 433 434 pinctrl_pcie: pciegrp { 435 fsl,pins = < 436 /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ 437 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ 438 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ 439 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ 440 >; 441 }; 442 443 pinctrl_pwm1: pwm1grp { 444 fsl,pins = < 445 /* 100 k PD, DSE 120 OHM, SPPEED LO */ 446 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 447 >; 448 }; 449 450 pinctrl_pwm3: pwm3grp { 451 fsl,pins = < 452 /* 100 k PD, DSE 120 OHM, SPPEED LO */ 453 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 454 >; 455 }; 456 457 pinctrl_pwm4: pwm4grp { 458 fsl,pins = < 459 /* 100 k PD, DSE 120 OHM, SPPEED LO */ 460 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 461 >; 462 }; 463 464 pinctrl_regpcie: regpciegrp { 465 fsl,pins = < 466 /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ 467 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ 468 >; 469 }; 470 471 pinctrl_uart2: uart2grp { 472 fsl,pins = < 473 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 474 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 475 >; 476 }; 477 478 pinctrl_uart3: uart3grp { 479 fsl,pins = < 480 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 481 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 482 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 483 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 484 >; 485 }; 486 487 pinctrl_uart4: uart4grp { 488 fsl,pins = < 489 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 490 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 491 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 492 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 493 >; 494 }; 495 496 pinctrl_uart5: uart5grp { 497 fsl,pins = < 498 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 499 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 500 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 501 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 502 >; 503 }; 504 505 pinctrl_usdhc2: usdhc2grp { 506 fsl,pins = < 507 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ 508 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 509 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ 510 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 511 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 512 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 513 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 514 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 515 516 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ 517 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ 518 >; 519 }; 520 521 pinctrl_usbotg: usbotggrp { 522 fsl,pins = < 523 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 524 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 525 MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 526 >; 527 }; 528 529 pinctrl_wdog1: wdog1grp { 530 fsl,pins = < 531 /* Watchdog out */ 532 MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 533 >; 534 }; 535}; 536