1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/leds/common.h>
7
8/ {
9	chosen {
10		stdout-path = &uart2;
11	};
12
13	aliases {
14		can0 = &can1;
15		can1 = &can2;
16		mdio-gpio0 = &mdio;
17		nand = &gpmi;
18		rtc0 = &i2c_rtc;
19		rtc1 = &snvs;
20		usb0 = &usbh1;
21		usb1 = &usbotg;
22	};
23
24	iio-hwmon {
25		compatible = "iio-hwmon";
26		io-channels = <&adc 0>, /* 24V */
27		              <&adc 1>; /* temperature */
28	};
29
30	leds {
31		compatible = "gpio-leds";
32
33		led-0 {
34			label = "D1";
35			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
36			function = LED_FUNCTION_STATUS;
37			default-state = "on";
38			linux,default-trigger = "heartbeat";
39		};
40
41		led-1 {
42			label = "D2";
43			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
44			default-state = "off";
45		};
46
47		led-2 {
48			label = "D3";
49			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
50			default-state = "on";
51		};
52	};
53
54	mdio: mdio {
55		compatible = "microchip,mdio-smi0";
56		pinctrl-names = "default";
57		pinctrl-0 = <&pinctrl_mdio>;
58		#address-cells = <1>;
59		#size-cells = <0>;
60		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
61			<&gpio1 22 GPIO_ACTIVE_HIGH>;
62
63		switch@0 {
64			compatible = "microchip,ksz8873";
65			pinctrl-names = "default";
66			pinctrl-0 = <&pinctrl_switch>;
67			interrupt-parent = <&gpio3>;
68			interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
69			reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
70			reg = <0>;
71
72			ports {
73				#address-cells = <1>;
74				#size-cells = <0>;
75
76				ports@0 {
77					reg = <0>;
78					phy-mode = "internal";
79					label = "lan1";
80				};
81
82				ports@1 {
83					reg = <1>;
84					phy-mode = "internal";
85					label = "lan2";
86				};
87
88				ports@2 {
89					reg = <2>;
90					label = "cpu";
91					ethernet = <&fec>;
92					phy-mode = "rmii";
93
94					fixed-link {
95						speed = <100>;
96						full-duplex;
97					};
98				};
99			};
100		};
101
102	};
103
104	clk50m_phy: phy-clock {
105		compatible = "fixed-clock";
106		#clock-cells = <0>;
107		clock-frequency = <50000000>;
108	};
109
110	reg_3v3: regulator-3v3 {
111		compatible = "regulator-fixed";
112		vin-supply = <&reg_5v0>;
113		regulator-name = "3v3";
114		regulator-min-microvolt = <3300000>;
115		regulator-max-microvolt = <3300000>;
116	};
117
118	reg_5v0: regulator-5v0 {
119		compatible = "regulator-fixed";
120		regulator-name = "5v0";
121		regulator-min-microvolt = <5000000>;
122		regulator-max-microvolt = <5000000>;
123	};
124
125	reg_24v0: regulator-24v0 {
126		compatible = "regulator-fixed";
127		regulator-name = "24v0";
128		regulator-min-microvolt = <24000000>;
129		regulator-max-microvolt = <24000000>;
130	};
131
132	reg_can1_stby: regulator-can1-stby {
133		compatible = "regulator-fixed";
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_can1_stby>;
136		regulator-name = "can1-3v3";
137		regulator-min-microvolt = <3300000>;
138		regulator-max-microvolt = <3300000>;
139		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
140	};
141
142	reg_can2_stby: regulator-can2-stby {
143		compatible = "regulator-fixed";
144		pinctrl-names = "default";
145		pinctrl-0 = <&pinctrl_can2_stby>;
146		regulator-name = "can2-3v3";
147		regulator-min-microvolt = <3300000>;
148		regulator-max-microvolt = <3300000>;
149		gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
150	};
151
152	reg_tft_vcom: regulator-tft-vcom {
153		compatible = "pwm-regulator";
154		pwms = <&pwm3 0 20000 0>;
155		regulator-name = "tft_vcom";
156		regulator-min-microvolt = <3600000>;
157		regulator-max-microvolt = <3600000>;
158		regulator-always-on;
159		voltage-table = <3600000 26>;
160	};
161
162	reg_vcc_mmc: regulator-vcc-mmc {
163		compatible = "regulator-fixed";
164		pinctrl-names = "default";
165		pinctrl-0 = <&pinctrl_vcc_mmc>;
166		vin-supply = <&reg_3v3>;
167		regulator-name = "mmc_vcc_supply";
168		regulator-min-microvolt = <3300000>;
169		regulator-max-microvolt = <3300000>;
170		regulator-always-on;
171		regulator-boot-on;
172		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
173		enable-active-high;
174		startup-delay-us = <100>;
175	};
176
177	reg_vcc_mmc_io: regulator-vcc-mmc-io {
178		compatible = "regulator-gpio";
179		pinctrl-names = "default";
180		pinctrl-0 = <&pinctrl_vcc_mmc_io>;
181		vin-supply = <&reg_5v0>;
182		regulator-name = "mmc_io_supply";
183		regulator-type = "voltage";
184		regulator-min-microvolt = <1800000>;
185		regulator-max-microvolt = <3300000>;
186		gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
187		enable-active-high;
188		states = <1800000 0x1>, <3300000 0x0>;
189		startup-delay-us = <100>;
190	};
191};
192
193&can1 {
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_can1>;
196	xceiver-supply = <&reg_can1_stby>;
197	status = "okay";
198};
199
200&can2 {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_can2>;
203	xceiver-supply = <&reg_can2_stby>;
204	status = "okay";
205};
206
207&ecspi1 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_ecspi1>;
210	cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
211	status = "okay";
212
213	flash@0 {
214		compatible = "jedec,spi-nor";
215		spi-max-frequency = <54000000>;
216		reg = <0>;
217	};
218};
219
220&ecspi2 {
221	pinctrl-names = "default";
222	pinctrl-0 = <&pinctrl_ecspi2>;
223	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
224	status = "okay";
225
226	adc: adc@0 {
227		compatible = "microchip,mcp3002";
228		reg = <0>;
229		vref-supply = <&reg_3v3>;
230		spi-max-frequency = <1000000>;
231		#io-channel-cells = <1>;
232	};
233};
234
235&fec {
236	pinctrl-names = "default";
237	pinctrl-0 = <&pinctrl_enet>;
238	clocks = <&clks IMX6QDL_CLK_ENET>,
239		 <&clks IMX6QDL_CLK_ENET>,
240		 <&clk50m_phy>;
241	clock-names = "ipg", "ahb", "ptp";
242	phy-mode = "rmii";
243	phy-supply = <&reg_3v3>;
244	status = "okay";
245
246	fixed-link {
247		speed = <100>;
248		full-duplex;
249	};
250};
251
252&gpmi {
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_gpmi_nand>;
255	nand-on-flash-bbt;
256	#address-cells = <1>;
257	#size-cells = <0>;
258	status = "okay";
259};
260
261&i2c3 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&pinctrl_i2c3>;
264	clock-frequency = <400000>;
265	status = "okay";
266
267	i2c_rtc: rtc@51 {
268		compatible = "nxp,pcf85063";
269		reg = <0x51>;
270		quartz-load-femtofarads = <12500>;
271	};
272};
273
274&pwm2 {
275	pinctrl-names = "default";
276	pinctrl-0 = <&pinctrl_pwm2>;
277	#pwm-cells = <2>;
278	status = "okay";
279};
280
281&pwm3 {
282	/* used for LCD contrast control */
283	pinctrl-names = "default";
284	pinctrl-0 = <&pinctrl_pwm3>;
285	status = "okay";
286};
287
288&uart2 {
289	pinctrl-names = "default";
290	pinctrl-0 = <&pinctrl_uart2>;
291	status = "okay";
292};
293
294&usbh1 {
295	vbus-supply = <&reg_5v0>;
296	disable-over-current;
297	status = "okay";
298};
299
300/* no usbh2 */
301&usbphynop1 {
302	status = "disabled";
303};
304
305/* no usbh3 */
306&usbphynop2 {
307	status = "disabled";
308};
309
310&usbotg {
311	vbus-supply = <&reg_5v0>;
312	disable-over-current;
313	status = "okay";
314};
315
316&usdhc3 {
317	pinctrl-names = "default";
318	pinctrl-0 = <&pinctrl_usdhc3>;
319	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
320	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
321	cap-power-off-card;
322	full-pwr-cycle;
323	bus-width = <4>;
324	max-frequency = <50000000>;
325	cap-sd-highspeed;
326	sd-uhs-sdr12;
327	sd-uhs-sdr25;
328	sd-uhs-sdr50;
329	sd-uhs-ddr50;
330	mmc-ddr-1_8v;
331	vmmc-supply = <&reg_vcc_mmc>;
332	vqmmc-supply = <&reg_vcc_mmc_io>;
333	status = "okay";
334};
335
336&iomuxc {
337	pinctrl_can1: can1grp {
338		fsl,pins = <
339			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX			0x3008
340			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX			0x1b000
341		>;
342	};
343
344	pinctrl_can1_stby: can1stbygrp {
345		fsl,pins = <
346			MX6QDL_PAD_EIM_D31__GPIO3_IO31			0x13008
347		>;
348	};
349
350	pinctrl_can2: can2grp {
351		fsl,pins = <
352			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX		0x3008
353			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX		0x1b000
354		>;
355	};
356
357	pinctrl_can2_stby: can2stbygrp {
358		fsl,pins = <
359			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11			0x13008
360		>;
361	};
362
363	pinctrl_ecspi1: ecspi1grp {
364		fsl,pins = <
365			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x100b1
366			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0xb1
367			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0xb1
368			/* *no* external pull up */
369			MX6QDL_PAD_EIM_D24__GPIO3_IO24			0x58
370		>;
371	};
372
373	pinctrl_ecspi2: ecspi2grp {
374		fsl,pins = <
375			MX6QDL_PAD_EIM_OE__ECSPI2_MISO			0x100b1
376			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI			0xb1
377			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK			0xb1
378			/* external pull up */
379			MX6QDL_PAD_EIM_RW__GPIO2_IO26			0x58
380		>;
381	};
382
383	pinctrl_enet: enetgrp {
384		fsl,pins = <
385			/* RMII 50 MHz */
386			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x100f5
387			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x100f5
388			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x100c0
389			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x100c0
390			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x100f5
391			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x100f5
392			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0
393			MX6QDL_PAD_GPIO_5__GPIO1_IO05			0x58
394			/* GPIO for "link active" */
395			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24		0x3038
396		>;
397	};
398
399	pinctrl_gpmi_nand: gpminandgrp {
400		fsl,pins = <
401			MX6QDL_PAD_NANDF_CLE__NAND_CLE			0xb0b1
402			MX6QDL_PAD_NANDF_ALE__NAND_ALE			0xb0b1
403			MX6QDL_PAD_NANDF_RB0__NAND_READY_B		0xb000
404			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B		0xb0b1
405			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B		0xb0b1
406			MX6QDL_PAD_SD4_CMD__NAND_RE_B			0xb0b1
407			MX6QDL_PAD_SD4_CLK__NAND_WE_B			0xb0b1
408			MX6QDL_PAD_NANDF_D0__NAND_DATA00		0xb0b1
409			MX6QDL_PAD_NANDF_D1__NAND_DATA01		0xb0b1
410			MX6QDL_PAD_NANDF_D2__NAND_DATA02		0xb0b1
411			MX6QDL_PAD_NANDF_D3__NAND_DATA03		0xb0b1
412			MX6QDL_PAD_NANDF_D4__NAND_DATA04		0xb0b1
413			MX6QDL_PAD_NANDF_D5__NAND_DATA05		0xb0b1
414			MX6QDL_PAD_NANDF_D6__NAND_DATA06		0xb0b1
415			MX6QDL_PAD_NANDF_D7__NAND_DATA07		0xb0b1
416		>;
417	};
418
419	pinctrl_i2c3: i2c3grp {
420		fsl,pins = <
421			/* external 10 k pull up */
422			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x40010878
423			/* external 10 k pull up */
424			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x40010878
425		>;
426	};
427
428	pinctrl_mdio: mdiogrp {
429		fsl,pins = <
430			MX6QDL_PAD_ENET_MDIO__GPIO1_IO22		0x100b1
431			MX6QDL_PAD_ENET_MDC__GPIO1_IO31			0xb1
432		>;
433	};
434
435	pinctrl_pwm2: pwm2grp {
436		fsl,pins = <
437			MX6QDL_PAD_GPIO_1__PWM2_OUT			0x58
438		>;
439	};
440
441	pinctrl_pwm3: pwm3grp {
442		fsl,pins = <
443			MX6QDL_PAD_SD1_DAT1__PWM3_OUT			0x58
444		>;
445	};
446
447	pinctrl_switch: switchgrp {
448		fsl,pins = <
449			MX6QDL_PAD_EIM_D30__GPIO3_IO30			0xb0
450		>;
451	};
452
453	pinctrl_uart2: uart2grp {
454		fsl,pins = <
455			MX6QDL_PAD_EIM_D26__UART2_TX_DATA		0x1b0b1
456			MX6QDL_PAD_EIM_D27__UART2_RX_DATA		0x1b0b1
457		>;
458	};
459
460	pinctrl_usdhc3: usdhc3grp {
461		fsl,pins = <
462			/* SoC internal pull up required */
463			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17059
464			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10059
465			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17059
466			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17059
467			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17059
468			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17059
469			/* SoC internal pull up required */
470			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01			0x1b040
471			/* SoC internal pull up required */
472			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00			0x1b040
473		>;
474	};
475
476	pinctrl_vcc_mmc: vccmmcgrp {
477		fsl,pins = <
478			MX6QDL_PAD_SD3_RST__GPIO7_IO08			0x58
479		>;
480	};
481
482	pinctrl_vcc_mmc_io: vccmmciogrp {
483		fsl,pins = <
484			MX6QDL_PAD_GPIO_18__GPIO7_IO13			0x58
485		>;
486	};
487};
488