1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2018-2022 Toradex 4 */ 5 6#include "imx6ull.dtsi" 7 8/ { 9 /* Ethernet aliases to ensure correct MAC addresses */ 10 aliases { 11 ethernet0 = &fec2; 12 ethernet1 = &fec1; 13 }; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 4 8 16 32 64 128 255>; 18 default-brightness-level = <6>; 19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_3v3>; 23 pwms = <&pwm4 0 5000000 1>; 24 status = "disabled"; 25 }; 26 27 connector { 28 compatible = "gpio-usb-b-connector", "usb-b-connector"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_snvs_usbc_det>; 31 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ 32 label = "USBC"; 33 self-powered; 34 type = "micro"; 35 36 ports { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 port@0 { 41 reg = <0>; 42 usb_dr_connector: endpoint { 43 remote-endpoint = <&usb1_drd_sw>; 44 }; 45 }; 46 }; 47 }; 48 49 gpio-keys { 50 compatible = "gpio-keys"; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_snvs_gpiokeys>; 53 54 key-wakeup { 55 debounce-interval = <10>; 56 gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ 57 label = "Wake-Up"; 58 linux,code = <KEY_WAKEUP>; 59 wakeup-source; 60 }; 61 }; 62 63 panel_dpi: panel-dpi { 64 compatible = "edt,et057090dhu"; 65 backlight = <&backlight>; 66 power-supply = <®_3v3>; 67 status = "disabled"; 68 69 port { 70 lcd_panel_in: endpoint { 71 remote-endpoint = <&lcdif_out>; 72 }; 73 }; 74 }; 75 76 reg_module_3v3: regulator-module-3v3 { 77 compatible = "regulator-fixed"; 78 regulator-always-on; 79 regulator-name = "+V3.3"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 }; 83 84 reg_module_3v3_avdd: regulator-module-3v3-avdd { 85 compatible = "regulator-fixed"; 86 regulator-always-on; 87 regulator-name = "+V3.3_AVDD_AUDIO"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 }; 91 92 reg_sd1_vqmmc: regulator-sd1-vqmmc { 93 compatible = "regulator-gpio"; 94 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 97 regulator-always-on; 98 regulator-name = "+V3.3_1.8_SD"; 99 regulator-min-microvolt = <1800000>; 100 regulator-max-microvolt = <3300000>; 101 states = <1800000 0x1 3300000 0x0>; 102 vin-supply = <®_module_3v3>; 103 }; 104 105 reg_eth_phy: regulator-eth-phy { 106 compatible = "regulator-fixed-clock"; 107 regulator-boot-on; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 regulator-name = "+V3.3_ETH"; 111 regulator-type = "voltage"; 112 vin-supply = <®_module_3v3>; 113 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 114 startup-delay-us = <150000>; 115 }; 116}; 117 118&adc1 { 119 vref-supply = <®_module_3v3_avdd>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_adc1>; 122}; 123 124&can1 { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_flexcan1>; 127 status = "disabled"; 128}; 129 130&can2 { 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_flexcan2>; 133 status = "disabled"; 134}; 135 136/* Colibri SPI */ 137&ecspi1 { 138 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 141}; 142 143/* Ethernet */ 144&fec2 { 145 pinctrl-names = "default", "sleep"; 146 pinctrl-0 = <&pinctrl_enet2>; 147 pinctrl-1 = <&pinctrl_enet2_sleep>; 148 phy-mode = "rmii"; 149 phy-handle = <ðphy1>; 150 phy-supply = <®_eth_phy>; 151 status = "okay"; 152 153 mdio { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 ethphy1: ethernet-phy@2 { 158 compatible = "ethernet-phy-ieee802.3-c22"; 159 max-speed = <100>; 160 reg = <2>; 161 }; 162 }; 163}; 164 165/* NAND */ 166&gpmi { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_gpmi_nand>; 169 fsl,use-minimum-ecc; 170 nand-on-flash-bbt; 171 nand-ecc-mode = "hw"; 172 nand-ecc-strength = <8>; 173 nand-ecc-step-size = <512>; 174 status = "okay"; 175}; 176 177/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ 178&i2c1 { 179 pinctrl-names = "default", "gpio"; 180 pinctrl-0 = <&pinctrl_i2c1>; 181 pinctrl-1 = <&pinctrl_i2c1_gpio>; 182 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 183 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 184 status = "disabled"; 185 186 /* Atmel maxtouch controller */ 187 atmel_mxt_ts: touchscreen@4a { 188 compatible = "atmel,maxtouch"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; 191 reg = <0x4a>; 192 interrupt-parent = <&gpio5>; 193 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ 194 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ 195 status = "disabled"; 196 }; 197}; 198 199/* 200 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 201 * touch screen controller 202 */ 203&i2c2 { 204 /* Use low frequency to compensate for the high pull-up values. */ 205 clock-frequency = <40000>; 206 pinctrl-names = "default", "gpio"; 207 pinctrl-0 = <&pinctrl_i2c2>; 208 pinctrl-1 = <&pinctrl_i2c2_gpio>; 209 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 210 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 211 status = "okay"; 212 213 ad7879_ts: touchscreen@2c { 214 compatible = "adi,ad7879-1"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 217 reg = <0x2c>; 218 interrupt-parent = <&gpio5>; 219 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 220 touchscreen-max-pressure = <4096>; 221 adi,resistance-plate-x = <120>; 222 adi,first-conversion-delay = /bits/ 8 <3>; 223 adi,acquisition-time = /bits/ 8 <1>; 224 adi,median-filter-size = /bits/ 8 <2>; 225 adi,averaging = /bits/ 8 <1>; 226 adi,conversion-interval = /bits/ 8 <255>; 227 status = "disabled"; 228 }; 229}; 230 231&lcdif { 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_lcdif_dat 234 &pinctrl_lcdif_ctrl>; 235 status = "disabled"; 236 237 port { 238 lcdif_out: endpoint { 239 remote-endpoint = <&lcd_panel_in>; 240 }; 241 }; 242}; 243 244/* PWM <A> */ 245&pwm4 { 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_pwm4>; 248}; 249 250/* PWM <B> */ 251&pwm5 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_pwm5>; 254}; 255 256/* PWM <C> */ 257&pwm6 { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_pwm6>; 260}; 261 262/* PWM <D> */ 263&pwm7 { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_pwm7>; 266}; 267 268&sdma { 269 status = "okay"; 270}; 271 272&snvs_pwrkey { 273 status = "disabled"; 274}; 275 276/* Colibri UART_A */ 277&uart1 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 280 uart-has-rtscts; 281 fsl,dte-mode; 282}; 283 284/* Colibri UART_B */ 285&uart2 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_uart2>; 288 uart-has-rtscts; 289 fsl,dte-mode; 290}; 291 292/* Colibri UART_C */ 293&uart5 { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_uart5>; 296 fsl,dte-mode; 297}; 298 299/* Colibri USBC */ 300&usbotg1 { 301 dr_mode = "otg"; 302 srp-disable; 303 hnp-disable; 304 adp-disable; 305 usb-role-switch; 306 307 port { 308 usb1_drd_sw: endpoint { 309 remote-endpoint = <&usb_dr_connector>; 310 }; 311 }; 312}; 313 314/* Colibri USBH */ 315&usbotg2 { 316 dr_mode = "host"; 317}; 318 319/* Colibri MMC/SD */ 320&usdhc1 { 321 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 322 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 323 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 324 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 325 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; 326 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 327 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 328 assigned-clock-rates = <0>, <198000000>; 329 bus-width = <4>; 330 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 331 disable-wp; 332 keep-power-in-suspend; 333 no-1-8-v; 334 vqmmc-supply = <®_sd1_vqmmc>; 335 wakeup-source; 336}; 337 338&wdog1 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_wdog>; 341 fsl,ext-reset-output; 342}; 343 344&iomuxc { 345 pinctrl_adc1: adc1grp { 346 fsl,pins = < 347 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ 348 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ 349 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ 350 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ 351 >; 352 }; 353 354 pinctrl_atmel_adap: atmeladapgrp { 355 fsl,pins = < 356 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ 357 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ 358 >; 359 }; 360 361 pinctrl_atmel_conn: atmelconngrp { 362 fsl,pins = < 363 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ 364 >; 365 }; 366 367 pinctrl_can_int: canintgrp { 368 fsl,pins = < 369 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ 370 >; 371 }; 372 373 pinctrl_enet2: enet2grp { 374 fsl,pins = < 375 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 376 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 377 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 378 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 379 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 380 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 381 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 382 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 383 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 384 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 385 >; 386 }; 387 388 pinctrl_enet2_sleep: enet2-sleepgrp { 389 fsl,pins = < 390 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 391 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 392 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 393 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 394 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 395 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 396 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 397 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 398 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 399 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 400 >; 401 }; 402 403 pinctrl_ecspi1_cs: ecspi1csgrp { 404 fsl,pins = < 405 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ 406 >; 407 }; 408 409 pinctrl_ecspi1: ecspi1grp { 410 fsl,pins = < 411 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ 412 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ 413 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ 414 >; 415 }; 416 417 pinctrl_flexcan1: flexcan1grp { 418 fsl,pins = < 419 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 420 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 421 >; 422 }; 423 424 pinctrl_flexcan2: flexcan2grp { 425 fsl,pins = < 426 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 427 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 428 >; 429 }; 430 431 pinctrl_gpio_bl_on: gpioblongrp { 432 fsl,pins = < 433 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ 434 >; 435 }; 436 437 pinctrl_gpio1: gpio1grp { 438 fsl,pins = < 439 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ 440 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ 441 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ 442 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ 443 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ 444 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ 445 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ 446 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ 447 >; 448 }; 449 450 pinctrl_gpio2: gpio2grp { /* Camera */ 451 fsl,pins = < 452 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ 453 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ 454 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ 455 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ 456 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ 457 >; 458 }; 459 460 pinctrl_gpio3: gpio3grp { /* CAN2 */ 461 fsl,pins = < 462 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ 463 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ 464 >; 465 }; 466 467 pinctrl_gpio4: gpio4grp { 468 fsl,pins = < 469 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ 470 >; 471 }; 472 473 pinctrl_gpio6: gpio6grp { /* Wifi pins */ 474 fsl,pins = < 475 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ 476 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ 477 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ 478 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ 479 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ 480 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ 481 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ 482 >; 483 }; 484 485 pinctrl_gpio7: gpio7grp { /* CAN1 */ 486 fsl,pins = < 487 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ 488 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ 489 >; 490 }; 491 492 /* 493 * With an eMMC instead of a raw NAND device the following pins 494 * are available at SODIMM pins. 495 */ 496 pinctrl_gpmi_gpio: gpmigpiogrp { 497 fsl,pins = < 498 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ 499 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ 500 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ 501 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ 502 >; 503 }; 504 505 pinctrl_gpmi_nand: gpminandgrp { 506 fsl,pins = < 507 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 508 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 509 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 510 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 511 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 512 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 513 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 514 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 515 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 516 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 517 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 518 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 519 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 520 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 521 >; 522 }; 523 524 pinctrl_i2c1: i2c1grp { 525 fsl,pins = < 526 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ 527 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ 528 >; 529 }; 530 531 pinctrl_i2c1_gpio: i2c1-gpiogrp { 532 fsl,pins = < 533 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ 534 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ 535 >; 536 }; 537 538 pinctrl_i2c2: i2c2grp { 539 fsl,pins = < 540 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 541 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 542 >; 543 }; 544 545 pinctrl_i2c2_gpio: i2c2-gpiogrp { 546 fsl,pins = < 547 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 548 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 549 >; 550 }; 551 552 pinctrl_lcdif_dat: lcdifdatgrp { 553 fsl,pins = < 554 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ 555 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ 556 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ 557 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ 558 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ 559 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ 560 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ 561 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ 562 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ 563 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ 564 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ 565 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ 566 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ 567 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ 568 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ 569 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ 570 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ 571 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ 572 >; 573 }; 574 575 pinctrl_lcdif_ctrl: lcdifctrlgrp { 576 fsl,pins = < 577 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ 578 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ 579 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ 580 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ 581 >; 582 }; 583 584 pinctrl_pwm4: pwm4grp { 585 fsl,pins = < 586 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ 587 >; 588 }; 589 590 pinctrl_pwm5: pwm5grp { 591 fsl,pins = < 592 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ 593 >; 594 }; 595 596 pinctrl_pwm6: pwm6grp { 597 fsl,pins = < 598 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ 599 >; 600 }; 601 602 pinctrl_pwm7: pwm7grp { 603 fsl,pins = < 604 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ 605 >; 606 }; 607 608 pinctrl_uart1: uart1grp { 609 fsl,pins = < 610 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ 611 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ 612 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ 613 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ 614 >; 615 }; 616 617 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ 618 fsl,pins = < 619 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ 620 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ 621 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ 622 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ 623 >; 624 }; 625 626 pinctrl_uart2: uart2grp { 627 fsl,pins = < 628 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ 629 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ 630 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ 631 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ 632 >; 633 }; 634 pinctrl_uart5: uart5grp { 635 fsl,pins = < 636 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ 637 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ 638 >; 639 }; 640 641 pinctrl_usbh_reg: usbhreggrp { 642 fsl,pins = < 643 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ 644 >; 645 }; 646 647 pinctrl_usdhc1: usdhc1grp { 648 fsl,pins = < 649 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ 650 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ 651 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ 652 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ 653 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ 654 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ 655 >; 656 }; 657 658 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 659 fsl,pins = < 660 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 661 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 662 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 663 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 664 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 665 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 666 >; 667 }; 668 669 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 670 fsl,pins = < 671 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 672 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 673 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 674 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 675 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 676 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 677 >; 678 }; 679 680 pinctrl_usdhc2: usdhc2grp { 681 fsl,pins = < 682 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 683 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 684 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 685 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 686 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 687 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 688 689 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 690 >; 691 }; 692 693 pinctrl_usdhc2emmc: usdhc2emmcgrp { 694 fsl,pins = < 695 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 696 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 697 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 698 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 699 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 700 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 701 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 702 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 703 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 704 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 705 >; 706 }; 707 708 pinctrl_wdog: wdoggrp { 709 fsl,pins = < 710 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 711 >; 712 }; 713}; 714 715&iomuxc_snvs { 716 pinctrl_atmel_snvs_conn: atmelsnvsconngrp { 717 fsl,pins = < 718 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ 719 >; 720 }; 721 722 pinctrl_snvs_gpio1: snvsgpio1grp { 723 fsl,pins = < 724 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ 725 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ 726 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ 727 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ 728 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ 729 >; 730 }; 731 732 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ 733 fsl,pins = < 734 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ 735 >; 736 }; 737 738 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ 739 fsl,pins = < 740 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 741 >; 742 }; 743 744 pinctrl_snvs_reg_sd: snvsregsdgrp { 745 fsl,pins = < 746 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 747 >; 748 }; 749 750 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 751 fsl,pins = < 752 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 753 >; 754 }; 755 756 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { 757 fsl,pins = < 758 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ 759 >; 760 }; 761 762 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { 763 fsl,pins = < 764 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ 765 >; 766 }; 767 768 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { 769 fsl,pins = < 770 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 771 >; 772 }; 773 774 pinctrl_snvs_wifi_pdn: snvswifipdngrp { 775 fsl,pins = < 776 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 777 >; 778 }; 779}; 780