1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include "imx7d.dtsi" 8 9/ { 10 model = "Freescale i.MX7 SabreSD Board"; 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 13 chosen { 14 stdout-path = &uart1; 15 }; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio_keys>; 26 27 key-volume-up { 28 label = "Volume Up"; 29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 30 linux,code = <KEY_VOLUMEUP>; 31 wakeup-source; 32 }; 33 34 key-volume-down { 35 label = "Volume Down"; 36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 37 linux,code = <KEY_VOLUMEDOWN>; 38 wakeup-source; 39 }; 40 }; 41 42 spi-4 { 43 compatible = "spi-gpio"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_spi4>; 46 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 47 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 49 num-chipselects = <1>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 extended_io: gpio-expander@0 { 54 compatible = "fairchild,74hc595"; 55 gpio-controller; 56 #gpio-cells = <2>; 57 reg = <0>; 58 registers-number = <1>; 59 spi-max-frequency = <100000>; 60 }; 61 }; 62 63 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 64 compatible = "regulator-fixed"; 65 regulator-name = "usb_otg1_vbus"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 73 compatible = "regulator-fixed"; 74 regulator-name = "usb_otg2_vbus"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_vref_1v8: regulator-vref-1v8 { 84 compatible = "regulator-fixed"; 85 regulator-name = "vref-1v8"; 86 regulator-min-microvolt = <1800000>; 87 regulator-max-microvolt = <1800000>; 88 }; 89 90 reg_brcm: regulator-brcm { 91 compatible = "regulator-fixed"; 92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 regulator-name = "brcm_reg"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_brcm_reg>; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 startup-delay-us = <200000>; 100 }; 101 102 reg_lcd_3v3: regulator-lcd-3v3 { 103 compatible = "regulator-fixed"; 104 regulator-name = "lcd-3v3"; 105 regulator-min-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>; 107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 108 }; 109 110 reg_can2_3v3: regulator-can2-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "can2-3v3"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_flexcan2_reg>; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 118 }; 119 120 reg_fec2_3v3: regulator-fec2-3v3 { 121 compatible = "regulator-fixed"; 122 regulator-name = "fec2-3v3"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_enet2_reg>; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 128 }; 129 130 backlight: backlight { 131 compatible = "pwm-backlight"; 132 pwms = <&pwm1 0 5000000 0>; 133 brightness-levels = <0 4 8 16 32 64 128 255>; 134 default-brightness-level = <6>; 135 status = "okay"; 136 }; 137 138 panel { 139 compatible = "innolux,at043tn24"; 140 backlight = <&backlight>; 141 power-supply = <®_lcd_3v3>; 142 143 port { 144 panel_in: endpoint { 145 remote-endpoint = <&display_out>; 146 }; 147 }; 148 }; 149 150 sound { 151 compatible = "fsl,imx7d-evk-wm8960", 152 "fsl,imx-audio-wm8960"; 153 model = "wm8960-audio"; 154 audio-cpu = <&sai1>; 155 audio-codec = <&codec>; 156 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; 157 audio-routing = 158 "Headphone Jack", "HP_L", 159 "Headphone Jack", "HP_R", 160 "Ext Spk", "SPK_LP", 161 "Ext Spk", "SPK_LN", 162 "Ext Spk", "SPK_RP", 163 "Ext Spk", "SPK_RN", 164 "LINPUT1", "AMIC", 165 "AMIC", "MICB"; 166 }; 167 168 sound-hdmi { 169 compatible = "fsl,imx-audio-sii902x"; 170 model = "sii902x-audio"; 171 audio-cpu = <&sai3>; 172 hdmi-out; 173 }; 174}; 175 176&adc1 { 177 vref-supply = <®_vref_1v8>; 178 status = "okay"; 179}; 180 181&adc2 { 182 vref-supply = <®_vref_1v8>; 183 status = "okay"; 184}; 185 186&cpu0 { 187 cpu-supply = <&sw1a_reg>; 188}; 189 190&cpu1 { 191 cpu-supply = <&sw1a_reg>; 192}; 193 194&ecspi3 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_ecspi3>; 197 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 198 status = "okay"; 199 200 tsc2046@0 { 201 compatible = "ti,tsc2046"; 202 reg = <0>; 203 spi-max-frequency = <1000000>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 206 interrupt-parent = <&gpio2>; 207 interrupts = <29 0>; 208 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 209 touchscreen-max-pressure = <255>; 210 wakeup-source; 211 }; 212}; 213 214&fec1 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_enet1>; 217 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 218 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 219 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 220 assigned-clock-rates = <0>, <100000000>; 221 phy-mode = "rgmii"; 222 phy-handle = <ðphy0>; 223 fsl,magic-packet; 224 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 225 status = "okay"; 226 227 mdio { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 ethphy0: ethernet-phy@0 { 232 reg = <0>; 233 }; 234 235 ethphy1: ethernet-phy@1 { 236 reg = <1>; 237 }; 238 }; 239}; 240 241&fec2 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_enet2>; 244 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 245 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 246 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 247 assigned-clock-rates = <0>, <100000000>; 248 phy-mode = "rgmii"; 249 phy-handle = <ðphy1>; 250 phy-supply = <®_fec2_3v3>; 251 fsl,magic-packet; 252 status = "okay"; 253}; 254 255&flexcan2 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_flexcan2>; 258 xceiver-supply = <®_can2_3v3>; 259 status = "okay"; 260}; 261 262&i2c1 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_i2c1>; 265 status = "okay"; 266 267 pmic: pfuze3000@8 { 268 compatible = "fsl,pfuze3000"; 269 reg = <0x08>; 270 271 regulators { 272 sw1a_reg: sw1a { 273 regulator-min-microvolt = <700000>; 274 regulator-max-microvolt = <1475000>; 275 regulator-boot-on; 276 regulator-always-on; 277 regulator-ramp-delay = <6250>; 278 }; 279 280 /* use sw1c_reg to align with pfuze100/pfuze200 */ 281 sw1c_reg: sw1b { 282 regulator-min-microvolt = <700000>; 283 regulator-max-microvolt = <1475000>; 284 regulator-boot-on; 285 regulator-always-on; 286 regulator-ramp-delay = <6250>; 287 }; 288 289 sw2_reg: sw2 { 290 regulator-min-microvolt = <1800000>; 291 regulator-max-microvolt = <1800000>; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 sw3a_reg: sw3 { 297 regulator-min-microvolt = <900000>; 298 regulator-max-microvolt = <1650000>; 299 regulator-boot-on; 300 regulator-always-on; 301 }; 302 303 swbst_reg: swbst { 304 regulator-min-microvolt = <5000000>; 305 regulator-max-microvolt = <5150000>; 306 }; 307 308 snvs_reg: vsnvs { 309 regulator-min-microvolt = <1000000>; 310 regulator-max-microvolt = <3000000>; 311 regulator-boot-on; 312 regulator-always-on; 313 }; 314 315 vref_reg: vrefddr { 316 regulator-boot-on; 317 regulator-always-on; 318 }; 319 320 vgen1_reg: vldo1 { 321 regulator-min-microvolt = <1800000>; 322 regulator-max-microvolt = <3300000>; 323 regulator-always-on; 324 }; 325 326 vgen2_reg: vldo2 { 327 regulator-min-microvolt = <800000>; 328 regulator-max-microvolt = <1550000>; 329 }; 330 331 vgen3_reg: vccsd { 332 regulator-min-microvolt = <2850000>; 333 regulator-max-microvolt = <3300000>; 334 regulator-always-on; 335 }; 336 337 vgen4_reg: v33 { 338 regulator-min-microvolt = <2850000>; 339 regulator-max-microvolt = <3300000>; 340 regulator-always-on; 341 }; 342 343 vgen5_reg: vldo3 { 344 regulator-min-microvolt = <1800000>; 345 regulator-max-microvolt = <3300000>; 346 regulator-always-on; 347 }; 348 349 vgen6_reg: vldo4 { 350 regulator-min-microvolt = <2800000>; 351 regulator-max-microvolt = <2800000>; 352 regulator-always-on; 353 }; 354 }; 355 }; 356}; 357 358&i2c2 { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_i2c2>; 361 status = "okay"; 362 363 mpl3115@60 { 364 compatible = "fsl,mpl3115"; 365 reg = <0x60>; 366 }; 367}; 368 369&i2c3 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_i2c3>; 372 status = "okay"; 373}; 374 375&i2c4 { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_i2c4>; 378 status = "okay"; 379 380 codec: wm8960@1a { 381 compatible = "wlf,wm8960"; 382 reg = <0x1a>; 383 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 384 clock-names = "mclk"; 385 wlf,shared-lrclk; 386 wlf,hp-cfg = <2 2 3>; 387 wlf,gpio-cfg = <1 3>; 388 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 389 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 390 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 391 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 392 assigned-clock-rates = <0>, <884736000>, <12288000>; 393 }; 394}; 395 396&lcdif { 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pinctrl_lcdif>; 399 status = "okay"; 400 401 port { 402 display_out: endpoint { 403 remote-endpoint = <&panel_in>; 404 }; 405 }; 406}; 407 408&pcie { 409 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 410 status = "okay"; 411}; 412 413®_1p0d { 414 vin-supply = <&sw2_reg>; 415}; 416 417®_1p2 { 418 vin-supply = <&sw2_reg>; 419}; 420 421&sai1 { 422 pinctrl-names = "default"; 423 pinctrl-0 = <&pinctrl_sai1>; 424 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 425 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 426 <&clks IMX7D_SAI1_ROOT_CLK>; 427 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 428 assigned-clock-rates = <0>, <884736000>, <36864000>; 429 status = "okay"; 430}; 431 432&sai3 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; 435 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, 436 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 437 <&clks IMX7D_SAI3_ROOT_CLK>; 438 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 439 assigned-clock-rates = <0>, <884736000>, <36864000>; 440 status = "okay"; 441}; 442 443&snvs_pwrkey { 444 status = "okay"; 445}; 446 447&uart1 { 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_uart1>; 450 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 451 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 452 status = "okay"; 453}; 454 455&uart6 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_uart6>; 458 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 459 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 460 uart-has-rtscts; 461 status = "okay"; 462}; 463 464&usbotg1 { 465 vbus-supply = <®_usb_otg1_vbus>; 466 status = "okay"; 467}; 468 469&usbotg2 { 470 vbus-supply = <®_usb_otg2_vbus>; 471 dr_mode = "host"; 472 status = "okay"; 473}; 474 475&usdhc1 { 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_usdhc1>; 478 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 479 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 480 wakeup-source; 481 keep-power-in-suspend; 482 status = "okay"; 483}; 484 485&usdhc2 { 486 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 487 pinctrl-0 = <&pinctrl_usdhc2>; 488 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 489 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 490 wakeup-source; 491 keep-power-in-suspend; 492 non-removable; 493 vmmc-supply = <®_brcm>; 494 fsl,tuning-step = <2>; 495 status = "okay"; 496}; 497 498&usdhc3 { 499 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 500 pinctrl-0 = <&pinctrl_usdhc3>; 501 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 502 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 503 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 504 assigned-clock-rates = <400000000>; 505 bus-width = <8>; 506 fsl,tuning-step = <2>; 507 non-removable; 508 status = "okay"; 509}; 510 511&wdog1 { 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pinctrl_wdog>; 514 fsl,ext-reset-output; 515}; 516 517&iomuxc { 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_hog>; 520 521 imx7d-sdb { 522 pinctrl_brcm_reg: brcmreggrp { 523 fsl,pins = < 524 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 525 >; 526 }; 527 528 pinctrl_ecspi3: ecspi3grp { 529 fsl,pins = < 530 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 531 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 532 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 533 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 534 >; 535 }; 536 537 pinctrl_enet1: enet1grp { 538 fsl,pins = < 539 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 540 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 541 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 542 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 543 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 544 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 545 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 546 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 547 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 548 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 549 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 550 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 551 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 552 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 553 >; 554 }; 555 556 pinctrl_enet2: enet2grp { 557 fsl,pins = < 558 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 559 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 560 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 561 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 562 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 563 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 564 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 565 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 566 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 567 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 568 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 569 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 570 >; 571 }; 572 573 pinctrl_enet2_reg: enet2reggrp { 574 fsl,pins = < 575 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 576 >; 577 }; 578 579 pinctrl_flexcan2: flexcan2grp { 580 fsl,pins = < 581 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 582 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 583 >; 584 }; 585 586 pinctrl_flexcan2_reg: flexcan2reggrp { 587 fsl,pins = < 588 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 589 >; 590 }; 591 592 pinctrl_gpio_keys: gpio_keysgrp { 593 fsl,pins = < 594 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 595 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 596 >; 597 }; 598 599 pinctrl_hog: hoggrp { 600 fsl,pins = < 601 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 602 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ 603 >; 604 }; 605 606 pinctrl_i2c1: i2c1grp { 607 fsl,pins = < 608 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 609 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 610 >; 611 }; 612 613 pinctrl_i2c2: i2c2grp { 614 fsl,pins = < 615 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 616 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 617 >; 618 }; 619 620 pinctrl_i2c3: i2c3grp { 621 fsl,pins = < 622 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 623 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 624 >; 625 }; 626 627 pinctrl_i2c4: i2c4grp { 628 fsl,pins = < 629 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 630 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 631 >; 632 }; 633 634 pinctrl_lcdif: lcdifgrp { 635 fsl,pins = < 636 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 637 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 638 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 639 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 640 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 641 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 642 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 643 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 644 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 645 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 646 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 647 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 648 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 649 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 650 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 651 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 652 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 653 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 654 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 655 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 656 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 657 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 658 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 659 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 660 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 661 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 662 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 663 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 664 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 665 >; 666 }; 667 668 pinctrl_sai1: sai1grp { 669 fsl,pins = < 670 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 671 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 672 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f 673 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 674 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f 675 >; 676 }; 677 678 pinctrl_sai2: sai2grp { 679 fsl,pins = < 680 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 681 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 682 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 683 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 684 >; 685 }; 686 687 pinctrl_sai3: sai3grp { 688 fsl,pins = < 689 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 690 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 691 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 692 >; 693 }; 694 695 pinctrl_spi4: spi4grp { 696 fsl,pins = < 697 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 698 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 699 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 700 >; 701 }; 702 703 pinctrl_tsc2046_pendown: tsc2046_pendown { 704 fsl,pins = < 705 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 706 >; 707 }; 708 709 pinctrl_uart1: uart1grp { 710 fsl,pins = < 711 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 712 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 713 >; 714 }; 715 716 pinctrl_uart5: uart5grp { 717 fsl,pins = < 718 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 719 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 720 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 721 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 722 >; 723 }; 724 725 pinctrl_uart6: uart6grp { 726 fsl,pins = < 727 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 728 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 729 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 730 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 731 >; 732 }; 733 734 pinctrl_usdhc1: usdhc1grp { 735 fsl,pins = < 736 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 737 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 738 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 739 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 740 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 741 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 742 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 743 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 744 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 745 >; 746 }; 747 748 pinctrl_usdhc2: usdhc2grp { 749 fsl,pins = < 750 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 751 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 752 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 753 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 754 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 755 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 756 >; 757 }; 758 759 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 760 fsl,pins = < 761 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 762 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 763 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 764 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 765 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 766 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 767 >; 768 }; 769 770 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 771 fsl,pins = < 772 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 773 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 774 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 775 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 776 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 777 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 778 >; 779 }; 780 781 782 pinctrl_usdhc3: usdhc3grp { 783 fsl,pins = < 784 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 785 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 786 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 787 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 788 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 789 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 790 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 791 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 792 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 793 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 794 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 795 >; 796 }; 797 798 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 799 fsl,pins = < 800 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 801 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 802 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 803 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 804 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 805 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 806 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 807 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 808 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 809 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 810 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 811 >; 812 }; 813 814 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 815 fsl,pins = < 816 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 817 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 818 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 819 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 820 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 821 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 822 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 823 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 824 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 825 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 826 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 827 >; 828 }; 829 }; 830}; 831 832&pwm1 { 833 pinctrl-names = "default"; 834 pinctrl-0 = <&pinctrl_pwm1>; 835 status = "okay"; 836}; 837 838&iomuxc_lpsr { 839 pinctrl_wdog: wdoggrp { 840 fsl,pins = < 841 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 842 >; 843 }; 844 845 pinctrl_pwm1: pwm1grp { 846 fsl,pins = < 847 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 848 >; 849 }; 850 851 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { 852 fsl,pins = < 853 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 854 >; 855 }; 856 857 pinctrl_sai3_mclk: sai3grp_mclk { 858 fsl,pins = < 859 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f 860 >; 861 }; 862}; 863