1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Common device tree for IGEP boards based on AM/DM37x
4 *
5 * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
6 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
7 */
8/dts-v1/;
9
10#include "omap36xx.dtsi"
11
12/ {
13	memory@80000000 {
14		device_type = "memory";
15		reg = <0x80000000 0x20000000>; /* 512 MB */
16	};
17
18	chosen {
19		stdout-path = &uart3;
20	};
21
22	sound {
23		compatible = "ti,omap-twl4030";
24		ti,model = "igep2";
25		ti,mcbsp = <&mcbsp2>;
26	};
27
28	vdd33: regulator-vdd33 {
29		compatible = "regulator-fixed";
30		regulator-name = "vdd33";
31		regulator-always-on;
32	};
33
34};
35
36&omap3_pmx_core {
37	gpmc_pins: pinmux_gpmc_pins {
38		pinctrl-single,pins = <
39			/* OneNAND seems to require PIN_INPUT on clock. */
40                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
41		>;
42	};
43
44	uart1_pins: pinmux_uart1_pins {
45		pinctrl-single,pins = <
46			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)	/* uart1_rx.uart1_rx */
47			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)	/* uart1_tx.uart1_tx */
48		>;
49	};
50
51	uart3_pins: pinmux_uart3_pins {
52		pinctrl-single,pins = <
53			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)	/* uart3_rx.uart3_rx */
54			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)	/* uart3_tx.uart3_tx */
55		>;
56	};
57
58	mcbsp2_pins: pinmux_mcbsp2_pins {
59		pinctrl-single,pins = <
60			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)	/* mcbsp2_fsx.mcbsp2_fsx */
61			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)	/* mcbsp2_clkx.mcbsp2_clkx */
62			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)	/* mcbsp2_dr.mcbsp2.dr */
63			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)	/* mcbsp2_dx.mcbsp2_dx */
64		>;
65	};
66
67	mmc1_pins: pinmux_mmc1_pins {
68		pinctrl-single,pins = <
69			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
70			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
71			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
72			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
73			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
74			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
75		>;
76	};
77
78	mmc2_pins: pinmux_mmc2_pins {
79		pinctrl-single,pins = <
80			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
81			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
82			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
83			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat1.sdmmc2_dat1 */
84			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
85			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
86		>;
87	};
88
89	i2c1_pins: pinmux_i2c1_pins {
90		pinctrl-single,pins = <
91			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
92			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
93		>;
94	};
95
96	i2c3_pins: pinmux_i2c3_pins {
97		pinctrl-single,pins = <
98			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl.i2c3_scl */
99			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda.i2c3_sda */
100		>;
101	};
102};
103
104&gpmc {
105	pinctrl-names = "default";
106	pinctrl-0 = <&gpmc_pins>;
107
108	nand@0,0 {
109		compatible = "ti,omap2-nand";
110		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
111		interrupt-parent = <&gpmc>;
112		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
113			     <1 IRQ_TYPE_NONE>;	/* termcount */
114		linux,mtd-name = "micron,mt29c4g96maz";
115		nand-bus-width = <16>;
116		gpmc,device-width = <2>;
117		ti,nand-ecc-opt = "bch8";
118
119		gpmc,sync-clk-ps = <0>;
120		gpmc,cs-on-ns = <0>;
121		gpmc,cs-rd-off-ns = <44>;
122		gpmc,cs-wr-off-ns = <44>;
123		gpmc,adv-on-ns = <6>;
124		gpmc,adv-rd-off-ns = <34>;
125		gpmc,adv-wr-off-ns = <44>;
126		gpmc,we-off-ns = <40>;
127		gpmc,oe-off-ns = <54>;
128		gpmc,access-ns = <64>;
129		gpmc,rd-cycle-ns = <82>;
130		gpmc,wr-cycle-ns = <82>;
131		gpmc,wr-access-ns = <40>;
132		gpmc,wr-data-mux-bus-ns = <0>;
133
134		#address-cells = <1>;
135		#size-cells = <1>;
136
137		status = "okay";
138	};
139
140	onenand@0,0 {
141		compatible = "ti,omap2-onenand";
142		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
143
144		gpmc,sync-read;
145		gpmc,sync-write;
146		gpmc,burst-length = <16>;
147		gpmc,burst-wrap;
148		gpmc,burst-read;
149		gpmc,burst-write;
150		gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
151		gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
152		gpmc,cs-on-ns = <0>;
153		gpmc,cs-rd-off-ns = <96>;
154		gpmc,cs-wr-off-ns = <96>;
155		gpmc,adv-on-ns = <0>;
156		gpmc,adv-rd-off-ns = <12>;
157		gpmc,adv-wr-off-ns = <12>;
158		gpmc,oe-on-ns = <18>;
159		gpmc,oe-off-ns = <96>;
160		gpmc,we-on-ns = <0>;
161		gpmc,we-off-ns = <96>;
162		gpmc,rd-cycle-ns = <114>;
163		gpmc,wr-cycle-ns = <114>;
164		gpmc,access-ns = <90>;
165		gpmc,page-burst-access-ns = <12>;
166		gpmc,bus-turnaround-ns = <0>;
167		gpmc,cycle2cycle-delay-ns = <0>;
168		gpmc,wait-monitoring-ns = <0>;
169		gpmc,clk-activation-ns = <6>;
170		gpmc,wr-data-mux-bus-ns = <30>;
171		gpmc,wr-access-ns = <90>;
172		gpmc,sync-clk-ps = <12000>;
173
174		#address-cells = <1>;
175		#size-cells = <1>;
176
177		status = "disabled";
178	};
179};
180
181&i2c1 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&i2c1_pins>;
184	clock-frequency = <2600000>;
185
186	twl: twl@48 {
187		reg = <0x48>;
188		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
189		interrupt-parent = <&intc>;
190
191		twl_audio: audio {
192			compatible = "ti,twl4030-audio";
193			codec {
194			};
195		};
196	};
197};
198
199#include "twl4030.dtsi"
200#include "twl4030_omap3.dtsi"
201
202&i2c3 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&i2c3_pins>;
205};
206
207&mcbsp2 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&mcbsp2_pins>;
210	status = "okay";
211};
212
213&mmc1 {
214	pinctrl-names = "default";
215	pinctrl-0 = <&mmc1_pins>;
216	vmmc-supply = <&vmmc1>;
217	vmmc_aux-supply = <&vsim>;
218	bus-width = <4>;
219	cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
220};
221
222&mmc3 {
223	status = "disabled";
224};
225
226&uart1 {
227	pinctrl-names = "default";
228	pinctrl-0 = <&uart1_pins>;
229};
230
231&uart3 {
232	pinctrl-names = "default";
233	pinctrl-0 = <&uart3_pins>;
234};
235
236&twl_gpio {
237	ti,use-leds;
238};
239
240&usb_otg_hs {
241	interface-type = <0>;
242	usb-phy = <&usb2_phy>;
243	phys = <&usb2_phy>;
244	phy-names = "usb2-phy";
245	mode = <3>;
246	power = <50>;
247};
248