1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
4 *
5 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/oxsemi,ox820.h>
10#include <dt-bindings/reset/oxsemi,ox820.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	compatible = "oxsemi,ox820";
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20		enable-method = "oxsemi,ox820-smp";
21
22		cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,arm11mpcore";
25			clocks = <&armclk>;
26			reg = <0>;
27		};
28
29		cpu@1 {
30			device_type = "cpu";
31			compatible = "arm,arm11mpcore";
32			clocks = <&armclk>;
33			reg = <1>;
34		};
35	};
36
37	memory {
38		device_type = "memory";
39		/* Max 512MB @ 0x60000000 */
40		reg = <0x60000000 0x20000000>;
41	};
42
43	clocks {
44		osc: oscillator {
45			compatible = "fixed-clock";
46			#clock-cells = <0>;
47			clock-frequency = <25000000>;
48		};
49
50		gmacclk: gmacclk {
51			compatible = "fixed-clock";
52			#clock-cells = <0>;
53			clock-frequency = <125000000>;
54		};
55
56		sysclk: sysclk {
57			compatible = "fixed-factor-clock";
58			#clock-cells = <0>;
59			clock-div = <4>;
60			clock-mult = <1>;
61			clocks = <&osc>;
62		};
63
64		plla: plla {
65			compatible = "fixed-clock";
66			#clock-cells = <0>;
67			clock-frequency = <850000000>;
68		};
69
70		armclk: armclk {
71			compatible = "fixed-factor-clock";
72			#clock-cells = <0>;
73			clock-div = <2>;
74			clock-mult = <1>;
75			clocks = <&plla>;
76		};
77	};
78
79	soc {
80		#address-cells = <1>;
81		#size-cells = <1>;
82		compatible = "simple-bus";
83		ranges;
84		interrupt-parent = <&gic>;
85
86		nandc: nand-controller@41000000 {
87			compatible = "oxsemi,ox820-nand";
88			reg = <0x41000000 0x100000>;
89			clocks = <&stdclk CLK_820_NAND>;
90			resets = <&reset RESET_NAND>;
91			#address-cells = <1>;
92			#size-cells = <0>;
93			status = "disabled";
94		};
95
96		etha: ethernet@40400000 {
97			compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
98			reg = <0x40400000 0x2000>;
99			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
100				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
101			interrupt-names = "macirq", "eth_wake_irq";
102			mac-address = [000000000000]; /* Filled in by U-Boot */
103			phy-mode = "rgmii";
104
105			clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
106			clock-names = "gmac", "stmmaceth";
107			resets = <&reset RESET_MAC>;
108
109			/* Regmap for sys registers */
110			oxsemi,sys-ctrl = <&sys>;
111
112			status = "disabled";
113		};
114
115		apb-bridge@44000000 {
116			#address-cells = <1>;
117			#size-cells = <1>;
118			compatible = "simple-bus";
119			ranges = <0 0x44000000 0x1000000>;
120
121			pinctrl: pinctrl {
122				compatible = "oxsemi,ox820-pinctrl";
123
124				/* Regmap for sys registers */
125				oxsemi,sys-ctrl = <&sys>;
126
127				pinctrl_uart0: uart0 {
128					uart0 {
129						pins = "gpio30", "gpio31";
130						function = "fct5";
131					};
132				};
133
134				pinctrl_uart0_modem: uart0_modem {
135					uart0_modem_a {
136						pins = "gpio24", "gpio24", "gpio26", "gpio27";
137						function = "fct4";
138					};
139					uart0_modem_b {
140						pins = "gpio28", "gpio29";
141						function = "fct5";
142					};
143				};
144
145				pinctrl_uart1: uart1 {
146					uart1 {
147						pins = "gpio7", "gpio8";
148						function = "fct4";
149					};
150				};
151
152				pinctrl_uart1_modem: uart1_modem {
153					uart1_modem {
154						pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
155						function = "fct4";
156					};
157				};
158
159				pinctrl_etha_mdio: etha_mdio {
160					etha_mdio {
161						pins = "gpio3", "gpio4";
162						function = "fct1";
163					};
164				};
165
166				pinctrl_nand: nand {
167					nand {
168						pins = "gpio12", "gpio13", "gpio14", "gpio15",
169						     "gpio16", "gpio17", "gpio18", "gpio19",
170						     "gpio20", "gpio21", "gpio22", "gpio23",
171						     "gpio24";
172						function = "fct1";
173					};
174				};
175			};
176
177			gpio0: gpio@0 {
178				compatible = "oxsemi,ox820-gpio";
179				reg = <0x000000 0x100000>;
180				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
181				#gpio-cells = <2>;
182				gpio-controller;
183				interrupt-controller;
184				#interrupt-cells = <2>;
185				ngpios = <32>;
186				oxsemi,gpio-bank = <0>;
187				gpio-ranges = <&pinctrl 0 0 32>;
188			};
189
190			gpio1: gpio@100000 {
191				compatible = "oxsemi,ox820-gpio";
192				reg = <0x100000 0x100000>;
193				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
194				#gpio-cells = <2>;
195				gpio-controller;
196				interrupt-controller;
197				#interrupt-cells = <2>;
198				ngpios = <18>;
199				oxsemi,gpio-bank = <1>;
200				gpio-ranges = <&pinctrl 0 32 18>;
201			};
202
203			uart0: serial@200000 {
204			       compatible = "ns16550a";
205			       reg = <0x200000 0x100000>;
206			       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
207			       reg-shift = <0>;
208			       fifo-size = <16>;
209			       reg-io-width = <1>;
210			       current-speed = <115200>;
211			       no-loopback-test;
212			       status = "disabled";
213			       clocks = <&sysclk>;
214			       resets = <&reset RESET_UART1>;
215			};
216
217			uart1: serial@300000 {
218			       compatible = "ns16550a";
219			       reg = <0x200000 0x100000>;
220			       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
221			       reg-shift = <0>;
222			       fifo-size = <16>;
223			       reg-io-width = <1>;
224			       current-speed = <115200>;
225			       no-loopback-test;
226			       status = "disabled";
227			       clocks = <&sysclk>;
228			       resets = <&reset RESET_UART2>;
229			};
230
231			rps@400000 {
232				#address-cells = <1>;
233				#size-cells = <1>;
234				compatible = "simple-bus";
235				ranges = <0 0x400000 0x100000>;
236
237				intc: interrupt-controller@0 {
238					compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
239					interrupt-controller;
240					reg = <0 0x200>;
241					interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
242					#interrupt-cells = <1>;
243					valid-mask = <0xffffffff>;
244					clear-mask = <0xffffffff>;
245				};
246
247				timer0: timer@200 {
248					compatible = "oxsemi,ox820-rps-timer";
249					reg = <0x200 0x40>;
250					clocks = <&sysclk>;
251					interrupt-parent = <&intc>;
252					interrupts = <4>;
253				};
254			};
255
256			sys: sys-ctrl@e00000 {
257				compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
258				reg = <0xe00000 0x200000>;
259
260				reset: reset-controller {
261					compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
262					#reset-cells = <1>;
263				};
264
265				stdclk: stdclk {
266					compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
267					#clock-cells = <1>;
268				};
269			};
270		};
271
272		apb-bridge@47000000 {
273			#address-cells = <1>;
274			#size-cells = <1>;
275			compatible = "simple-bus";
276			ranges = <0 0x47000000 0x1000000>;
277
278			scu: scu@0 {
279				compatible = "arm,arm11mp-scu";
280				reg = <0x0 0x100>;
281			};
282
283			local-timer@600 {
284				compatible = "arm,arm11mp-twd-timer";
285				reg = <0x600 0x20>;
286				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
287				clocks = <&armclk>;
288			};
289
290			gic: interrupt-controller@1000 {
291				compatible = "arm,arm11mp-gic";
292				interrupt-controller;
293				#interrupt-cells = <3>;
294				reg = <0x1000 0x1000>,
295				      <0x100 0x500>;
296			};
297		};
298	};
299};
300