1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/clock/qcom,lcc-msm8960.h> 7#include <dt-bindings/mfd/qcom-rpm.h> 8#include <dt-bindings/soc/qcom,gsbi.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 model = "Qualcomm MSM8960"; 14 compatible = "qcom,msm8960"; 15 interrupt-parent = <&intc>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 interrupts = <GIC_PPI 14 0x304>; 21 22 cpu@0 { 23 compatible = "qcom,krait"; 24 enable-method = "qcom,kpss-acc-v1"; 25 device_type = "cpu"; 26 reg = <0>; 27 next-level-cache = <&L2>; 28 qcom,acc = <&acc0>; 29 qcom,saw = <&saw0>; 30 }; 31 32 cpu@1 { 33 compatible = "qcom,krait"; 34 enable-method = "qcom,kpss-acc-v1"; 35 device_type = "cpu"; 36 reg = <1>; 37 next-level-cache = <&L2>; 38 qcom,acc = <&acc1>; 39 qcom,saw = <&saw1>; 40 }; 41 42 L2: l2-cache { 43 compatible = "cache"; 44 cache-level = <2>; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 reg = <0x0 0x0>; 51 }; 52 53 cpu-pmu { 54 compatible = "qcom,krait-pmu"; 55 interrupts = <GIC_PPI 10 0x304>; 56 qcom,no-pc-write; 57 }; 58 59 clocks { 60 cxo_board: cxo_board { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <19200000>; 64 clock-output-names = "cxo_board"; 65 }; 66 67 pxo_board: pxo_board { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <27000000>; 71 clock-output-names = "pxo_board"; 72 }; 73 74 sleep_clk { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <32768>; 78 clock-output-names = "sleep_clk"; 79 }; 80 }; 81 82 /* Temporary fixed regulator */ 83 vsdcc_fixed: vsdcc-regulator { 84 compatible = "regulator-fixed"; 85 regulator-name = "SDCC Power"; 86 regulator-min-microvolt = <2700000>; 87 regulator-max-microvolt = <2700000>; 88 regulator-always-on; 89 }; 90 91 soc: soc { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 compatible = "simple-bus"; 96 97 intc: interrupt-controller@2000000 { 98 compatible = "qcom,msm-qgic2"; 99 interrupt-controller; 100 #interrupt-cells = <3>; 101 reg = <0x02000000 0x1000>, 102 <0x02002000 0x1000>; 103 }; 104 105 timer@200a000 { 106 compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", 107 "qcom,msm-timer"; 108 interrupts = <GIC_PPI 1 0x301>, 109 <GIC_PPI 2 0x301>, 110 <GIC_PPI 3 0x301>; 111 reg = <0x0200a000 0x100>; 112 clock-frequency = <27000000>; 113 cpu-offset = <0x80000>; 114 }; 115 116 msmgpio: pinctrl@800000 { 117 compatible = "qcom,msm8960-pinctrl"; 118 gpio-controller; 119 gpio-ranges = <&msmgpio 0 0 152>; 120 #gpio-cells = <2>; 121 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 reg = <0x800000 0x4000>; 125 }; 126 127 gcc: clock-controller@900000 { 128 compatible = "qcom,gcc-msm8960"; 129 #clock-cells = <1>; 130 #power-domain-cells = <1>; 131 #reset-cells = <1>; 132 reg = <0x900000 0x4000>; 133 clocks = <&cxo_board>, 134 <&pxo_board>, 135 <&lcc PLL4>; 136 clock-names = "cxo", "pxo", "pll4"; 137 }; 138 139 lcc: clock-controller@28000000 { 140 compatible = "qcom,lcc-msm8960"; 141 reg = <0x28000000 0x1000>; 142 #clock-cells = <1>; 143 #reset-cells = <1>; 144 clocks = <&pxo_board>, 145 <&gcc PLL4_VOTE>, 146 <0>, 147 <0>, <0>, 148 <0>, <0>, 149 <0>; 150 clock-names = "pxo", 151 "pll4_vote", 152 "mi2s_codec_clk", 153 "codec_i2s_mic_codec_clk", 154 "spare_i2s_mic_codec_clk", 155 "codec_i2s_spkr_codec_clk", 156 "spare_i2s_spkr_codec_clk", 157 "pcm_codec_clk"; 158 }; 159 160 clock-controller@4000000 { 161 compatible = "qcom,mmcc-msm8960"; 162 reg = <0x4000000 0x1000>; 163 #clock-cells = <1>; 164 #power-domain-cells = <1>; 165 #reset-cells = <1>; 166 clocks = <&pxo_board>, 167 <&gcc PLL3>, 168 <&gcc PLL8_VOTE>, 169 <0>, 170 <0>, 171 <0>, 172 <0>, 173 <0>; 174 clock-names = "pxo", 175 "pll3", 176 "pll8_vote", 177 "dsi1pll", 178 "dsi1pllbyte", 179 "dsi2pll", 180 "dsi2pllbyte", 181 "hdmipll"; 182 }; 183 184 l2cc: clock-controller@2011000 { 185 compatible = "qcom,kpss-gcc", "syscon"; 186 reg = <0x2011000 0x1000>; 187 }; 188 189 rpm: rpm@108000 { 190 compatible = "qcom,rpm-msm8960"; 191 reg = <0x108000 0x1000>; 192 qcom,ipc = <&l2cc 0x8 2>; 193 194 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 195 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 196 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 197 interrupt-names = "ack", "err", "wakeup"; 198 199 regulators { 200 compatible = "qcom,rpm-pm8921-regulators"; 201 }; 202 }; 203 204 acc0: clock-controller@2088000 { 205 compatible = "qcom,kpss-acc-v1"; 206 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 207 }; 208 209 acc1: clock-controller@2098000 { 210 compatible = "qcom,kpss-acc-v1"; 211 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 212 }; 213 214 saw0: regulator@2089000 { 215 compatible = "qcom,saw2"; 216 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 217 regulator; 218 }; 219 220 saw1: regulator@2099000 { 221 compatible = "qcom,saw2"; 222 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 223 regulator; 224 }; 225 226 gsbi5: gsbi@16400000 { 227 compatible = "qcom,gsbi-v1.0.0"; 228 cell-index = <5>; 229 reg = <0x16400000 0x100>; 230 clocks = <&gcc GSBI5_H_CLK>; 231 clock-names = "iface"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 236 syscon-tcsr = <&tcsr>; 237 238 gsbi5_serial: serial@16440000 { 239 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 240 reg = <0x16440000 0x1000>, 241 <0x16400000 0x1000>; 242 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 244 clock-names = "core", "iface"; 245 status = "disabled"; 246 }; 247 }; 248 249 ssbi@500000 { 250 compatible = "qcom,ssbi"; 251 reg = <0x500000 0x1000>; 252 qcom,controller-type = "pmic-arbiter"; 253 254 pmicintc: pmic { 255 compatible = "qcom,pm8921"; 256 interrupt-parent = <&msmgpio>; 257 interrupts = <104 IRQ_TYPE_LEVEL_LOW>; 258 #interrupt-cells = <2>; 259 interrupt-controller; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 pwrkey@1c { 264 compatible = "qcom,pm8921-pwrkey"; 265 reg = <0x1c>; 266 interrupt-parent = <&pmicintc>; 267 interrupts = <50 IRQ_TYPE_EDGE_RISING>, 268 <51 IRQ_TYPE_EDGE_RISING>; 269 debounce = <15625>; 270 pull-up; 271 }; 272 273 keypad@148 { 274 compatible = "qcom,pm8921-keypad"; 275 reg = <0x148>; 276 interrupt-parent = <&pmicintc>; 277 interrupts = <74 IRQ_TYPE_EDGE_RISING>, 278 <75 IRQ_TYPE_EDGE_RISING>; 279 debounce = <15>; 280 scan-delay = <32>; 281 row-hold = <91500>; 282 }; 283 284 rtc@11d { 285 compatible = "qcom,pm8921-rtc"; 286 interrupt-parent = <&pmicintc>; 287 interrupts = <39 IRQ_TYPE_EDGE_RISING>; 288 reg = <0x11d>; 289 allow-set-time; 290 }; 291 }; 292 }; 293 294 rng@1a500000 { 295 compatible = "qcom,prng"; 296 reg = <0x1a500000 0x200>; 297 clocks = <&gcc PRNG_CLK>; 298 clock-names = "core"; 299 }; 300 301 sdcc3: mmc@12180000 { 302 compatible = "arm,pl18x", "arm,primecell"; 303 arm,primecell-periphid = <0x00051180>; 304 status = "disabled"; 305 reg = <0x12180000 0x8000>; 306 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 308 clock-names = "mclk", "apb_pclk"; 309 bus-width = <4>; 310 cap-sd-highspeed; 311 cap-mmc-highspeed; 312 max-frequency = <192000000>; 313 no-1-8-v; 314 vmmc-supply = <&vsdcc_fixed>; 315 }; 316 317 sdcc1: mmc@12400000 { 318 status = "disabled"; 319 compatible = "arm,pl18x", "arm,primecell"; 320 arm,primecell-periphid = <0x00051180>; 321 reg = <0x12400000 0x8000>; 322 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 324 clock-names = "mclk", "apb_pclk"; 325 bus-width = <8>; 326 max-frequency = <96000000>; 327 non-removable; 328 cap-sd-highspeed; 329 cap-mmc-highspeed; 330 vmmc-supply = <&vsdcc_fixed>; 331 }; 332 333 tcsr: syscon@1a400000 { 334 compatible = "qcom,tcsr-msm8960", "syscon"; 335 reg = <0x1a400000 0x100>; 336 }; 337 338 gsbi1: gsbi@16000000 { 339 compatible = "qcom,gsbi-v1.0.0"; 340 cell-index = <1>; 341 reg = <0x16000000 0x100>; 342 clocks = <&gcc GSBI1_H_CLK>; 343 clock-names = "iface"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges; 347 348 gsbi1_spi: spi@16080000 { 349 compatible = "qcom,spi-qup-v1.1.1"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0x16080000 0x1000>; 353 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 354 spi-max-frequency = <24000000>; 355 cs-gpios = <&msmgpio 8 0>; 356 357 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 358 clock-names = "core", "iface"; 359 status = "disabled"; 360 }; 361 }; 362 }; 363}; 364