1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX55 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2020, Linaro Ltd. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx55.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,sdx55.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; 21 interrupt-parent = <&intc>; 22 23 memory { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <38400000>; 33 clock-output-names = "xo_board"; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 42 nand_clk_dummy: nand-clk-dummy { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32000>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a7"; 56 reg = <0x0>; 57 enable-method = "psci"; 58 clocks = <&apcs>; 59 power-domains = <&rpmhpd SDX55_CX>; 60 power-domain-names = "rpmhpd"; 61 operating-points-v2 = <&cpu_opp_table>; 62 }; 63 }; 64 65 firmware { 66 scm { 67 compatible = "qcom,scm-sdx55", "qcom,scm"; 68 }; 69 }; 70 71 cpu_opp_table: opp-table-cpu { 72 compatible = "operating-points-v2"; 73 opp-shared; 74 75 opp-345600000 { 76 opp-hz = /bits/ 64 <345600000>; 77 required-opps = <&rpmhpd_opp_low_svs>; 78 }; 79 80 opp-576000000 { 81 opp-hz = /bits/ 64 <576000000>; 82 required-opps = <&rpmhpd_opp_svs>; 83 }; 84 85 opp-1094400000 { 86 opp-hz = /bits/ 64 <1094400000>; 87 required-opps = <&rpmhpd_opp_nom>; 88 }; 89 90 opp-1555200000 { 91 opp-hz = /bits/ 64 <1555200000>; 92 required-opps = <&rpmhpd_opp_turbo>; 93 }; 94 }; 95 96 psci { 97 compatible = "arm,psci-1.0"; 98 method = "smc"; 99 }; 100 101 reserved-memory { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges; 105 106 hyp_mem: memory@8fc00000 { 107 no-map; 108 reg = <0x8fc00000 0x80000>; 109 }; 110 111 ac_db_mem: memory@8fc80000 { 112 no-map; 113 reg = <0x8fc80000 0x40000>; 114 }; 115 116 secdata_mem: memory@8fcfd000 { 117 no-map; 118 reg = <0x8fcfd000 0x1000>; 119 }; 120 121 sbl_mem: memory@8fd00000 { 122 no-map; 123 reg = <0x8fd00000 0x100000>; 124 }; 125 126 aop_image: memory@8fe00000 { 127 no-map; 128 reg = <0x8fe00000 0x20000>; 129 }; 130 131 aop_cmd_db: memory@8fe20000 { 132 compatible = "qcom,cmd-db"; 133 reg = <0x8fe20000 0x20000>; 134 no-map; 135 }; 136 137 smem_mem: memory@8fe40000 { 138 no-map; 139 reg = <0x8fe40000 0xc0000>; 140 }; 141 142 tz_mem: memory@8ff00000 { 143 no-map; 144 reg = <0x8ff00000 0x100000>; 145 }; 146 147 tz_apps_mem: memory@90000000 { 148 no-map; 149 reg = <0x90000000 0x500000>; 150 }; 151 }; 152 153 smem { 154 compatible = "qcom,smem"; 155 memory-region = <&smem_mem>; 156 hwlocks = <&tcsr_mutex 3>; 157 }; 158 159 smp2p-mpss { 160 compatible = "qcom,smp2p"; 161 qcom,smem = <435>, <428>; 162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 163 mboxes = <&apcs 14>; 164 qcom,local-pid = <0>; 165 qcom,remote-pid = <1>; 166 167 modem_smp2p_out: master-kernel { 168 qcom,entry-name = "master-kernel"; 169 #qcom,smem-state-cells = <1>; 170 }; 171 172 modem_smp2p_in: slave-kernel { 173 qcom,entry-name = "slave-kernel"; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 }; 177 178 ipa_smp2p_out: ipa-ap-to-modem { 179 qcom,entry-name = "ipa"; 180 #qcom,smem-state-cells = <1>; 181 }; 182 183 ipa_smp2p_in: ipa-modem-to-ap { 184 qcom,entry-name = "ipa"; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 }; 188 }; 189 190 soc: soc { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges; 194 compatible = "simple-bus"; 195 196 gcc: clock-controller@100000 { 197 compatible = "qcom,gcc-sdx55"; 198 reg = <0x100000 0x1f0000>; 199 #clock-cells = <1>; 200 #reset-cells = <1>; 201 #power-domain-cells = <1>; 202 clock-names = "bi_tcxo", "sleep_clk"; 203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 204 }; 205 206 blsp1_uart3: serial@831000 { 207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 208 reg = <0x00831000 0x200>; 209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&gcc 30>, 211 <&gcc 9>; 212 clock-names = "core", "iface"; 213 status = "disabled"; 214 }; 215 216 usb_hsphy: phy@ff4000 { 217 compatible = "qcom,sdx55-usb-hs-phy", 218 "qcom,usb-snps-hs-7nm-phy"; 219 reg = <0x00ff4000 0x114>; 220 status = "disabled"; 221 #phy-cells = <0>; 222 223 clocks = <&rpmhcc RPMH_CXO_CLK>; 224 clock-names = "ref"; 225 226 resets = <&gcc GCC_QUSB2PHY_BCR>; 227 }; 228 229 usb_qmpphy: phy@ff6000 { 230 compatible = "qcom,sdx55-qmp-usb3-uni-phy"; 231 reg = <0x00ff6000 0x1c0>; 232 status = "disabled"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges; 236 237 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 238 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 239 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 240 clock-names = "aux", "cfg_ahb", "ref"; 241 242 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 243 <&gcc GCC_USB3_PHY_BCR>; 244 reset-names = "phy", "common"; 245 246 usb_ssphy: phy@ff6200 { 247 reg = <0x00ff6200 0x170>, 248 <0x00ff6400 0x200>, 249 <0x00ff6800 0x800>; 250 #phy-cells = <0>; 251 #clock-cells = <0>; 252 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 253 clock-names = "pipe0"; 254 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 255 }; 256 }; 257 258 mc_virt: interconnect@1100000 { 259 compatible = "qcom,sdx55-mc-virt"; 260 reg = <0x01100000 0x400000>; 261 #interconnect-cells = <1>; 262 qcom,bcm-voters = <&apps_bcm_voter>; 263 }; 264 265 mem_noc: interconnect@9680000 { 266 compatible = "qcom,sdx55-mem-noc"; 267 reg = <0x09680000 0x40000>; 268 #interconnect-cells = <1>; 269 qcom,bcm-voters = <&apps_bcm_voter>; 270 }; 271 272 system_noc: interconnect@162c000 { 273 compatible = "qcom,sdx55-system-noc"; 274 reg = <0x0162c000 0x31200>; 275 #interconnect-cells = <1>; 276 qcom,bcm-voters = <&apps_bcm_voter>; 277 }; 278 279 qpic_bam: dma-controller@1b04000 { 280 compatible = "qcom,bam-v1.7.0"; 281 reg = <0x01b04000 0x1c000>; 282 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&rpmhcc RPMH_QPIC_CLK>; 284 clock-names = "bam_clk"; 285 #dma-cells = <1>; 286 qcom,ee = <0>; 287 qcom,controlled-remotely; 288 status = "disabled"; 289 }; 290 291 qpic_nand: nand-controller@1b30000 { 292 compatible = "qcom,sdx55-nand"; 293 reg = <0x01b30000 0x10000>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 clocks = <&rpmhcc RPMH_QPIC_CLK>, 297 <&nand_clk_dummy>; 298 clock-names = "core", "aon"; 299 300 dmas = <&qpic_bam 0>, 301 <&qpic_bam 1>, 302 <&qpic_bam 2>; 303 dma-names = "tx", "rx", "cmd"; 304 status = "disabled"; 305 }; 306 307 pcie0_phy: phy@1c07000 { 308 compatible = "qcom,sdx55-qmp-pcie-phy"; 309 reg = <0x01c07000 0x1c4>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, 314 <&gcc GCC_PCIE_CFG_AHB_CLK>, 315 <&gcc GCC_PCIE_0_CLKREF_CLK>, 316 <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 317 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 318 319 resets = <&gcc GCC_PCIE_PHY_BCR>; 320 reset-names = "phy"; 321 322 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; 323 assigned-clock-rates = <100000000>; 324 325 status = "disabled"; 326 327 pcie0_lane: lanes@1c06000 { 328 reg = <0x01c06000 0x104>, /* tx0 */ 329 <0x01c06200 0x328>, /* rx0 */ 330 <0x01c07200 0x1e8>, /* pcs */ 331 <0x01c06800 0x104>, /* tx1 */ 332 <0x01c06a00 0x328>, /* rx1 */ 333 <0x01c07600 0x800>; /* pcs_misc */ 334 clocks = <&gcc GCC_PCIE_PIPE_CLK>; 335 clock-names = "pipe0"; 336 337 #phy-cells = <0>; 338 clock-output-names = "pcie_pipe_clk"; 339 }; 340 }; 341 342 ipa: ipa@1e40000 { 343 compatible = "qcom,sdx55-ipa"; 344 345 iommus = <&apps_smmu 0x5e0 0x0>, 346 <&apps_smmu 0x5e2 0x0>; 347 reg = <0x1e40000 0x7000>, 348 <0x1e50000 0x4b20>, 349 <0x1e04000 0x2c000>; 350 reg-names = "ipa-reg", 351 "ipa-shared", 352 "gsi"; 353 354 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 355 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 356 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 357 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 358 interrupt-names = "ipa", 359 "gsi", 360 "ipa-clock-query", 361 "ipa-setup-ready"; 362 363 clocks = <&rpmhcc RPMH_IPA_CLK>; 364 clock-names = "core"; 365 366 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>, 367 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, 368 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; 369 interconnect-names = "memory", 370 "imem", 371 "config"; 372 373 qcom,smem-states = <&ipa_smp2p_out 0>, 374 <&ipa_smp2p_out 1>; 375 qcom,smem-state-names = "ipa-clock-enabled-valid", 376 "ipa-clock-enabled"; 377 378 status = "disabled"; 379 }; 380 381 tcsr_mutex: hwlock@1f40000 { 382 compatible = "qcom,tcsr-mutex"; 383 reg = <0x01f40000 0x40000>; 384 #hwlock-cells = <1>; 385 }; 386 387 tcsr: syscon@1fcb000 { 388 compatible = "syscon"; 389 reg = <0x01fc0000 0x1000>; 390 }; 391 392 sdhc_1: mmc@8804000 { 393 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; 394 reg = <0x08804000 0x1000>; 395 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "hc_irq", "pwr_irq"; 398 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 399 <&gcc GCC_SDCC1_APPS_CLK>; 400 clock-names = "iface", "core"; 401 status = "disabled"; 402 }; 403 404 pcie_ep: pcie-ep@40000000 { 405 compatible = "qcom,sdx55-pcie-ep"; 406 reg = <0x01c00000 0x3000>, 407 <0x40000000 0xf1d>, 408 <0x40000f20 0xc8>, 409 <0x40001000 0x1000>, 410 <0x40200000 0x100000>, 411 <0x01c03000 0x3000>; 412 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 413 "mmio"; 414 415 qcom,perst-regs = <&tcsr 0xb258 0xb270>; 416 417 clocks = <&gcc GCC_PCIE_AUX_CLK>, 418 <&gcc GCC_PCIE_CFG_AHB_CLK>, 419 <&gcc GCC_PCIE_MSTR_AXI_CLK>, 420 <&gcc GCC_PCIE_SLV_AXI_CLK>, 421 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, 422 <&gcc GCC_PCIE_SLEEP_CLK>, 423 <&gcc GCC_PCIE_0_CLKREF_CLK>; 424 clock-names = "aux", "cfg", "bus_master", "bus_slave", 425 "slave_q2a", "sleep", "ref"; 426 427 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "global", "doorbell"; 430 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; 431 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; 432 resets = <&gcc GCC_PCIE_BCR>; 433 reset-names = "core"; 434 power-domains = <&gcc PCIE_GDSC>; 435 phys = <&pcie0_lane>; 436 phy-names = "pciephy"; 437 max-link-speed = <3>; 438 num-lanes = <2>; 439 440 status = "disabled"; 441 }; 442 443 remoteproc_mpss: remoteproc@4080000 { 444 compatible = "qcom,sdx55-mpss-pas"; 445 reg = <0x04080000 0x4040>; 446 447 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 448 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 449 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 450 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 451 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 452 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 453 interrupt-names = "wdog", "fatal", "ready", "handover", 454 "stop-ack", "shutdown-ack"; 455 456 clocks = <&rpmhcc RPMH_CXO_CLK>; 457 clock-names = "xo"; 458 459 power-domains = <&rpmhpd SDX55_CX>, 460 <&rpmhpd SDX55_MSS>; 461 power-domain-names = "cx", "mss"; 462 463 qcom,smem-states = <&modem_smp2p_out 0>; 464 qcom,smem-state-names = "stop"; 465 466 status = "disabled"; 467 468 glink-edge { 469 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 470 label = "mpss"; 471 qcom,remote-pid = <1>; 472 mboxes = <&apcs 15>; 473 }; 474 }; 475 476 usb: usb@a6f8800 { 477 compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; 478 reg = <0x0a6f8800 0x400>; 479 status = "disabled"; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 ranges; 483 484 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 485 <&gcc GCC_USB30_MASTER_CLK>, 486 <&gcc GCC_USB30_MSTR_AXI_CLK>, 487 <&gcc GCC_USB30_SLEEP_CLK>, 488 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 489 clock-names = "cfg_noc", 490 "core", 491 "iface", 492 "sleep", 493 "mock_utmi"; 494 495 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 496 <&gcc GCC_USB30_MASTER_CLK>; 497 assigned-clock-rates = <19200000>, <200000000>; 498 499 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "hs_phy_irq", "ss_phy_irq", 504 "dm_hs_phy_irq", "dp_hs_phy_irq"; 505 506 power-domains = <&gcc USB30_GDSC>; 507 508 resets = <&gcc GCC_USB30_BCR>; 509 510 usb_dwc3: dwc3@a600000 { 511 compatible = "snps,dwc3"; 512 reg = <0x0a600000 0xcd00>; 513 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 514 iommus = <&apps_smmu 0x1a0 0x0>; 515 snps,dis_u2_susphy_quirk; 516 snps,dis_enblslpm_quirk; 517 phys = <&usb_hsphy>, <&usb_ssphy>; 518 phy-names = "usb2-phy", "usb3-phy"; 519 }; 520 }; 521 522 pdc: interrupt-controller@b210000 { 523 compatible = "qcom,sdx55-pdc", "qcom,pdc"; 524 reg = <0x0b210000 0x30000>; 525 qcom,pdc-ranges = <0 179 52>; 526 #interrupt-cells = <3>; 527 interrupt-parent = <&intc>; 528 interrupt-controller; 529 }; 530 531 restart@c264000 { 532 compatible = "qcom,pshold"; 533 reg = <0x0c264000 0x1000>; 534 }; 535 536 spmi_bus: spmi@c440000 { 537 compatible = "qcom,spmi-pmic-arb"; 538 reg = <0x0c440000 0x0000d00>, 539 <0x0c600000 0x2000000>, 540 <0x0e600000 0x0100000>, 541 <0x0e700000 0x00a0000>, 542 <0x0c40a000 0x0000700>; 543 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 544 interrupt-names = "periph_irq"; 545 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 546 qcom,ee = <0>; 547 qcom,channel = <0>; 548 #address-cells = <2>; 549 #size-cells = <0>; 550 interrupt-controller; 551 #interrupt-cells = <4>; 552 cell-index = <0>; 553 }; 554 555 tlmm: pinctrl@f100000 { 556 compatible = "qcom,sdx55-pinctrl"; 557 reg = <0xf100000 0x300000>; 558 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 gpio-ranges = <&tlmm 0 0 108>; 564 }; 565 566 sram@1468f000 { 567 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; 568 reg = <0x1468f000 0x1000>; 569 570 #address-cells = <1>; 571 #size-cells = <1>; 572 573 ranges = <0x0 0x1468f000 0x1000>; 574 575 pil-reloc@94c { 576 compatible = "qcom,pil-reloc-info"; 577 reg = <0x94c 0x200>; 578 }; 579 }; 580 581 apps_smmu: iommu@15000000 { 582 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 583 reg = <0x15000000 0x20000>; 584 #iommu-cells = <2>; 585 #global-interrupts = <1>; 586 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 603 }; 604 605 intc: interrupt-controller@17800000 { 606 compatible = "qcom,msm-qgic2"; 607 interrupt-controller; 608 interrupt-parent = <&intc>; 609 #interrupt-cells = <3>; 610 reg = <0x17800000 0x1000>, 611 <0x17802000 0x1000>; 612 }; 613 614 a7pll: clock@17808000 { 615 compatible = "qcom,sdx55-a7pll"; 616 reg = <0x17808000 0x1000>; 617 clocks = <&rpmhcc RPMH_CXO_CLK>; 618 clock-names = "bi_tcxo"; 619 #clock-cells = <0>; 620 }; 621 622 apcs: mailbox@17810000 { 623 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 624 reg = <0x17810000 0x2000>; 625 #mbox-cells = <1>; 626 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 627 clock-names = "ref", "pll", "aux"; 628 #clock-cells = <0>; 629 }; 630 631 watchdog@17817000 { 632 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; 633 reg = <0x17817000 0x1000>; 634 clocks = <&sleep_clk>; 635 }; 636 637 timer@17820000 { 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges; 641 compatible = "arm,armv7-timer-mem"; 642 reg = <0x17820000 0x1000>; 643 clock-frequency = <19200000>; 644 645 frame@17821000 { 646 frame-number = <0>; 647 interrupts = <GIC_SPI 7 0x4>, 648 <GIC_SPI 6 0x4>; 649 reg = <0x17821000 0x1000>, 650 <0x17822000 0x1000>; 651 }; 652 653 frame@17823000 { 654 frame-number = <1>; 655 interrupts = <GIC_SPI 8 0x4>; 656 reg = <0x17823000 0x1000>; 657 status = "disabled"; 658 }; 659 660 frame@17824000 { 661 frame-number = <2>; 662 interrupts = <GIC_SPI 9 0x4>; 663 reg = <0x17824000 0x1000>; 664 status = "disabled"; 665 }; 666 667 frame@17825000 { 668 frame-number = <3>; 669 interrupts = <GIC_SPI 10 0x4>; 670 reg = <0x17825000 0x1000>; 671 status = "disabled"; 672 }; 673 674 frame@17826000 { 675 frame-number = <4>; 676 interrupts = <GIC_SPI 11 0x4>; 677 reg = <0x17826000 0x1000>; 678 status = "disabled"; 679 }; 680 681 frame@17827000 { 682 frame-number = <5>; 683 interrupts = <GIC_SPI 12 0x4>; 684 reg = <0x17827000 0x1000>; 685 status = "disabled"; 686 }; 687 688 frame@17828000 { 689 frame-number = <6>; 690 interrupts = <GIC_SPI 13 0x4>; 691 reg = <0x17828000 0x1000>; 692 status = "disabled"; 693 }; 694 695 frame@17829000 { 696 frame-number = <7>; 697 interrupts = <GIC_SPI 14 0x4>; 698 reg = <0x17829000 0x1000>; 699 status = "disabled"; 700 }; 701 }; 702 703 apps_rsc: rsc@17840000 { 704 compatible = "qcom,rpmh-rsc"; 705 reg = <0x17830000 0x10000>, <0x17840000 0x10000>; 706 reg-names = "drv-0", "drv-1"; 707 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 709 qcom,tcs-offset = <0xd00>; 710 qcom,drv-id = <1>; 711 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, 712 <WAKE_TCS 2>, <CONTROL_TCS 1>; 713 714 rpmhcc: clock-controller { 715 compatible = "qcom,sdx55-rpmh-clk"; 716 #clock-cells = <1>; 717 clock-names = "xo"; 718 clocks = <&xo_board>; 719 }; 720 721 rpmhpd: power-controller { 722 compatible = "qcom,sdx55-rpmhpd"; 723 #power-domain-cells = <1>; 724 operating-points-v2 = <&rpmhpd_opp_table>; 725 726 rpmhpd_opp_table: opp-table { 727 compatible = "operating-points-v2"; 728 729 rpmhpd_opp_ret: opp1 { 730 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 731 }; 732 733 rpmhpd_opp_min_svs: opp2 { 734 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 735 }; 736 737 rpmhpd_opp_low_svs: opp3 { 738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 739 }; 740 741 rpmhpd_opp_svs: opp4 { 742 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 743 }; 744 745 rpmhpd_opp_svs_l1: opp5 { 746 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 747 }; 748 749 rpmhpd_opp_nom: opp6 { 750 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 751 }; 752 753 rpmhpd_opp_nom_l1: opp7 { 754 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 755 }; 756 757 rpmhpd_opp_nom_l2: opp8 { 758 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 759 }; 760 761 rpmhpd_opp_turbo: opp9 { 762 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 763 }; 764 765 rpmhpd_opp_turbo_l1: opp10 { 766 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 767 }; 768 }; 769 }; 770 771 apps_bcm_voter: bcm-voter { 772 compatible = "qcom,bcm-voter"; 773 }; 774 }; 775 }; 776 777 timer { 778 compatible = "arm,armv7-timer"; 779 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 780 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 781 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 782 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 783 clock-frequency = <19200000>; 784 }; 785}; 786