1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron (and derivatives) board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8#include <dt-bindings/clock/rockchip,rk808.h>
9#include <dt-bindings/input/input.h>
10#include "rk3288.dtsi"
11
12/ {
13	chosen {
14		stdout-path = "serial2:115200n8";
15	};
16
17	/*
18	 * The default coreboot on veyron devices ignores memory@0 nodes
19	 * and would instead create another memory node.
20	 */
21	memory {
22		device_type = "memory";
23		reg = <0x0 0x0 0x0 0x80000000>;
24	};
25
26
27	power_button: power-button {
28		compatible = "gpio-keys";
29		pinctrl-names = "default";
30		pinctrl-0 = <&pwr_key_l>;
31
32		key-power {
33			label = "Power";
34			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
35			linux,code = <KEY_POWER>;
36			debounce-interval = <100>;
37			wakeup-source;
38		};
39	};
40
41	gpio-restart {
42		compatible = "gpio-restart";
43		gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
44		pinctrl-names = "default";
45		pinctrl-0 = <&ap_warm_reset_h>;
46		priority = <200>;
47	};
48
49	emmc_pwrseq: emmc-pwrseq {
50		compatible = "mmc-pwrseq-emmc";
51		pinctrl-0 = <&emmc_reset>;
52		pinctrl-names = "default";
53		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
54	};
55
56	sdio_pwrseq: sdio-pwrseq {
57		compatible = "mmc-pwrseq-simple";
58		clocks = <&rk808 RK808_CLKOUT1>;
59		clock-names = "ext_clock";
60		pinctrl-names = "default";
61		pinctrl-0 = <&wifi_enable_h>;
62
63		/*
64		 * Depending on the actual card populated GPIO4 D4
65		 * correspond to one of these signals on the module:
66		 *
67		 * D4:
68		 * - SDIO_RESET_L_WL_REG_ON
69		 * - PDN (power down when low)
70		 */
71		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
72	};
73
74	vcc_5v: vcc-5v {
75		compatible = "regulator-fixed";
76		regulator-name = "vcc_5v";
77		regulator-always-on;
78		regulator-boot-on;
79		regulator-min-microvolt = <5000000>;
80		regulator-max-microvolt = <5000000>;
81	};
82
83	vcc33_sys: vcc33-sys {
84		compatible = "regulator-fixed";
85		regulator-name = "vcc33_sys";
86		regulator-always-on;
87		regulator-boot-on;
88		regulator-min-microvolt = <3300000>;
89		regulator-max-microvolt = <3300000>;
90	};
91
92	vcc50_hdmi: vcc50-hdmi {
93		compatible = "regulator-fixed";
94		regulator-name = "vcc50_hdmi";
95		regulator-always-on;
96		regulator-boot-on;
97		vin-supply = <&vcc_5v>;
98	};
99
100	vdd_logic: vdd-logic {
101		compatible = "pwm-regulator";
102		regulator-name = "vdd_logic";
103
104		pwms = <&pwm1 0 1994 0>;
105		pwm-supply = <&vcc33_sys>;
106
107		pwm-dutycycle-range = <0x7b 0>;
108		pwm-dutycycle-unit = <0x94>;
109
110		regulator-always-on;
111		regulator-boot-on;
112		regulator-min-microvolt = <950000>;
113		regulator-max-microvolt = <1350000>;
114		regulator-ramp-delay = <4000>;
115	};
116};
117
118&cpu0 {
119	cpu0-supply = <&vdd_cpu>;
120};
121
122&cpu_crit {
123	temperature = <100000>;
124};
125
126/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
127&cpu_opp_table {
128	/delete-node/ opp-312000000;
129
130	opp-1512000000 {
131		opp-microvolt = <1250000>;
132	};
133	opp-1608000000 {
134		opp-microvolt = <1300000>;
135	};
136	opp-1704000000 {
137		opp-hz = /bits/ 64 <1704000000>;
138		opp-microvolt = <1350000>;
139	};
140	opp-1800000000 {
141		opp-hz = /bits/ 64 <1800000000>;
142		opp-microvolt = <1400000>;
143	};
144};
145
146&emmc {
147	status = "okay";
148
149	bus-width = <8>;
150	cap-mmc-highspeed;
151	rockchip,default-sample-phase = <158>;
152	disable-wp;
153	mmc-hs200-1_8v;
154	mmc-pwrseq = <&emmc_pwrseq>;
155	non-removable;
156	pinctrl-names = "default";
157	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
158};
159
160&gpu {
161	mali-supply = <&vdd_gpu>;
162	status = "okay";
163};
164
165&gpu_alert0 {
166	temperature = <72500>;
167};
168
169&gpu_crit {
170	temperature = <100000>;
171};
172
173&hdmi {
174	pinctrl-names = "default", "unwedge";
175	pinctrl-0 = <&hdmi_ddc>;
176	pinctrl-1 = <&hdmi_ddc_unwedge>;
177	status = "okay";
178};
179
180&i2c0 {
181	status = "okay";
182
183	clock-frequency = <400000>;
184	i2c-scl-falling-time-ns = <50>;		/* 2.5ns measured */
185	i2c-scl-rising-time-ns = <100>;		/* 45ns measured */
186
187	rk808: pmic@1b {
188		compatible = "rockchip,rk808";
189		reg = <0x1b>;
190		clock-output-names = "xin32k", "wifibt_32kin";
191		interrupt-parent = <&gpio0>;
192		interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
193		pinctrl-names = "default";
194		pinctrl-0 = <&pmic_int_l>;
195		rockchip,system-power-controller;
196		wakeup-source;
197		#clock-cells = <1>;
198
199		vcc1-supply = <&vcc33_sys>;
200		vcc2-supply = <&vcc33_sys>;
201		vcc3-supply = <&vcc33_sys>;
202		vcc4-supply = <&vcc33_sys>;
203		vcc6-supply = <&vcc_5v>;
204		vcc7-supply = <&vcc33_sys>;
205		vcc8-supply = <&vcc33_sys>;
206		vcc12-supply = <&vcc_18>;
207		vddio-supply = <&vcc33_io>;
208
209		regulators {
210			vdd_cpu: DCDC_REG1 {
211				regulator-name = "vdd_arm";
212				regulator-always-on;
213				regulator-boot-on;
214				regulator-min-microvolt = <750000>;
215				regulator-max-microvolt = <1450000>;
216				regulator-ramp-delay = <6001>;
217				regulator-state-mem {
218					regulator-off-in-suspend;
219				};
220			};
221
222			vdd_gpu: DCDC_REG2 {
223				regulator-name = "vdd_gpu";
224				regulator-always-on;
225				regulator-boot-on;
226				regulator-min-microvolt = <800000>;
227				regulator-max-microvolt = <1250000>;
228				regulator-ramp-delay = <6001>;
229				regulator-state-mem {
230					regulator-off-in-suspend;
231				};
232			};
233
234			vcc135_ddr: DCDC_REG3 {
235				regulator-name = "vcc135_ddr";
236				regulator-always-on;
237				regulator-boot-on;
238				regulator-state-mem {
239					regulator-on-in-suspend;
240				};
241			};
242
243			/*
244			 * vcc_18 has several aliases.  (vcc18_flashio and
245			 * vcc18_wl).  We'll add those aliases here just to
246			 * make it easier to follow the schematic.  The signals
247			 * are actually hooked together and only separated for
248			 * power measurement purposes).
249			 */
250			vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
251				regulator-name = "vcc_18";
252				regulator-always-on;
253				regulator-boot-on;
254				regulator-min-microvolt = <1800000>;
255				regulator-max-microvolt = <1800000>;
256				regulator-state-mem {
257					regulator-on-in-suspend;
258					regulator-suspend-microvolt = <1800000>;
259				};
260			};
261
262			/*
263			 * Note that both vcc33_io and vcc33_pmuio are always
264			 * powered together. To simplify the logic in the dts
265			 * we just refer to vcc33_io every time something is
266			 * powered from vcc33_pmuio. In fact, on later boards
267			 * (such as danger) they're the same net.
268			 */
269			vcc33_io: LDO_REG1 {
270				regulator-name = "vcc33_io";
271				regulator-always-on;
272				regulator-boot-on;
273				regulator-min-microvolt = <3300000>;
274				regulator-max-microvolt = <3300000>;
275				regulator-state-mem {
276					regulator-on-in-suspend;
277					regulator-suspend-microvolt = <3300000>;
278				};
279			};
280
281			vdd_10: LDO_REG3 {
282				regulator-name = "vdd_10";
283				regulator-always-on;
284				regulator-boot-on;
285				regulator-min-microvolt = <1000000>;
286				regulator-max-microvolt = <1000000>;
287				regulator-state-mem {
288					regulator-on-in-suspend;
289					regulator-suspend-microvolt = <1000000>;
290				};
291			};
292
293			vdd10_lcd_pwren_h: LDO_REG7 {
294				regulator-name = "vdd10_lcd_pwren_h";
295				regulator-always-on;
296				regulator-boot-on;
297				regulator-min-microvolt = <2500000>;
298				regulator-max-microvolt = <2500000>;
299				regulator-state-mem {
300					regulator-off-in-suspend;
301				};
302			};
303
304			vcc33_lcd: SWITCH_REG1 {
305				regulator-name = "vcc33_lcd";
306				regulator-always-on;
307				regulator-boot-on;
308				regulator-state-mem {
309					regulator-off-in-suspend;
310				};
311			};
312		};
313	};
314};
315
316&i2c1 {
317	status = "okay";
318
319	clock-frequency = <400000>;
320	i2c-scl-falling-time-ns = <50>;		/* 2.5ns measured */
321	i2c-scl-rising-time-ns = <100>;		/* 40ns measured */
322
323	tpm: tpm@20 {
324		compatible = "infineon,slb9645tt";
325		reg = <0x20>;
326		powered-while-suspended;
327	};
328};
329
330&i2c2 {
331	status = "okay";
332
333	/* 100kHz since 4.7k resistors don't rise fast enough */
334	clock-frequency = <100000>;
335	i2c-scl-falling-time-ns = <50>;		/* 10ns measured */
336	i2c-scl-rising-time-ns = <800>;		/* 600ns measured */
337};
338
339&i2c4 {
340	status = "okay";
341
342	clock-frequency = <400000>;
343	i2c-scl-falling-time-ns = <50>;		/* 11ns measured */
344	i2c-scl-rising-time-ns = <300>;		/* 225ns measured */
345};
346
347&io_domains {
348	status = "okay";
349
350	bb-supply = <&vcc33_io>;
351	dvp-supply = <&vcc_18>;
352	flash0-supply = <&vcc18_flashio>;
353	gpio1830-supply = <&vcc33_io>;
354	gpio30-supply = <&vcc33_io>;
355	lcdc-supply = <&vcc33_lcd>;
356	wifi-supply = <&vcc18_wl>;
357};
358
359&pwm1 {
360	status = "okay";
361};
362
363&sdio0 {
364	status = "okay";
365
366	bus-width = <4>;
367	cap-sd-highspeed;
368	cap-sdio-irq;
369	keep-power-in-suspend;
370	mmc-pwrseq = <&sdio_pwrseq>;
371	non-removable;
372	pinctrl-names = "default";
373	pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
374	sd-uhs-sdr12;
375	sd-uhs-sdr25;
376	sd-uhs-sdr50;
377	sd-uhs-sdr104;
378	vmmc-supply = <&vcc33_sys>;
379	vqmmc-supply = <&vcc18_wl>;
380};
381
382&spi2 {
383	status = "okay";
384
385	rx-sample-delay-ns = <12>;
386
387	flash@0 {
388		compatible = "jedec,spi-nor";
389		spi-max-frequency = <50000000>;
390		reg = <0>;
391	};
392};
393
394&tsadc {
395	status = "okay";
396
397	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
398	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
399	rockchip,hw-tshut-temp = <125000>;
400};
401
402&uart0 {
403	status = "okay";
404
405	/* Pins don't include flow control by default; add that in */
406	pinctrl-names = "default";
407	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
408};
409
410&uart1 {
411	status = "okay";
412};
413
414&uart2 {
415	status = "okay";
416};
417
418&usbphy {
419	status = "okay";
420};
421
422&usb_host0_ehci {
423	status = "okay";
424
425	needs-reset-on-resume;
426};
427
428&usb_host1 {
429	status = "okay";
430	snps,need-phy-for-wake;
431};
432
433&usb_otg {
434	status = "okay";
435
436	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
437	assigned-clock-parents = <&usbphy0>;
438	dr_mode = "host";
439	snps,need-phy-for-wake;
440};
441
442&vopb {
443	status = "okay";
444};
445
446&vopb_mmu {
447	status = "okay";
448};
449
450&wdt {
451	status = "okay";
452};
453
454&pinctrl {
455	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
456		bias-disable;
457		drive-strength = <8>;
458	};
459
460	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
461		bias-pull-up;
462		drive-strength = <8>;
463	};
464
465	pcfg_output_high: pcfg-output-high {
466		output-high;
467	};
468
469	pcfg_output_low: pcfg-output-low {
470		output-low;
471	};
472
473	buttons {
474		pwr_key_l: pwr-key-l {
475			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
476		};
477	};
478
479	emmc {
480		emmc_reset: emmc-reset {
481			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
482		};
483
484		/*
485		 * We run eMMC at max speed; bump up drive strength.
486		 * We also have external pulls, so disable the internal ones.
487		 */
488		emmc_clk: emmc-clk {
489			rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
490		};
491
492		emmc_cmd: emmc-cmd {
493			rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
494		};
495
496		emmc_bus8: emmc-bus8 {
497			rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
498					<3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
499					<3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
500					<3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
501					<3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
502					<3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
503					<3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
504					<3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
505		};
506	};
507
508	pmic {
509		pmic_int_l: pmic-int-l {
510			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
511		};
512	};
513
514	reboot {
515		ap_warm_reset_h: ap-warm-reset-h {
516			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
517		};
518	};
519
520	recovery-switch {
521		rec_mode_l: rec-mode-l {
522			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
523		};
524	};
525
526	sdio0 {
527		wifi_enable_h: wifienable-h {
528			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
529		};
530
531		/* NOTE: mislabelled on schematic; should be bt_enable_h */
532		bt_enable_l: bt-enable-l {
533			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
534		};
535
536		bt_host_wake: bt-host-wake {
537			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
538		};
539
540		bt_host_wake_l: bt-host-wake-l {
541			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
542		};
543
544		/*
545		 * We run sdio0 at max speed; bump up drive strength.
546		 * We also have external pulls, so disable the internal ones.
547		 */
548		sdio0_bus4: sdio0-bus4 {
549			rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
550					<4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
551					<4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
552					<4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
553		};
554
555		sdio0_cmd: sdio0-cmd {
556			rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
557		};
558
559		sdio0_clk: sdio0-clk {
560			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
561		};
562
563		/*
564		 * These pins are only present on very new veyron boards; on
565		 * older boards bt_dev_wake is simply always high.  Note that
566		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
567		 * to map this pin everywhere
568		 */
569		bt_dev_wake_sleep: bt-dev-wake-sleep {
570			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
571		};
572
573		bt_dev_wake_awake: bt-dev-wake-awake {
574			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
575		};
576
577		bt_dev_wake: bt-dev-wake {
578			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
579		};
580	};
581
582	tpm {
583		tpm_int_h: tpm-int-h {
584			rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
585		};
586	};
587
588	write-protect {
589		fw_wp_ap: fw-wp-ap {
590			rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
591		};
592	};
593};
594