1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <arm64/rockchip/rockchip-pinconf.dtsi>
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	clk_out_ethernet {
15		/omit-if-no-ref/
16		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17			rockchip,pins =
18				/* clk_out_ethernet_m1 */
19				<2 RK_PC5 2 &pcfg_pull_none>;
20		};
21	};
22	emmc {
23		/omit-if-no-ref/
24		emmc_rstnout: emmc-rstnout {
25			rockchip,pins =
26				/* emmc_rstn */
27				<1 RK_PA3 2 &pcfg_pull_none>;
28		};
29		/omit-if-no-ref/
30		emmc_bus8: emmc-bus8 {
31			rockchip,pins =
32				/* emmc_d0 */
33				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
34				/* emmc_d1 */
35				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
36				/* emmc_d2 */
37				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
38				/* emmc_d3 */
39				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
40				/* emmc_d4 */
41				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
42				/* emmc_d5 */
43				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
44				/* emmc_d6 */
45				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
46				/* emmc_d7 */
47				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
48		};
49		/omit-if-no-ref/
50		emmc_clk: emmc-clk {
51			rockchip,pins =
52				/* emmc_clko */
53				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
54		};
55		/omit-if-no-ref/
56		emmc_cmd: emmc-cmd {
57			rockchip,pins =
58				/* emmc_cmd */
59				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
60		};
61	};
62	i2c0 {
63		/omit-if-no-ref/
64		i2c0_xfer: i2c0-xfer {
65			rockchip,pins =
66				/* i2c0_scl */
67				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
68				/* i2c0_sda */
69				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
70		};
71	};
72	rgmii {
73		/omit-if-no-ref/
74		rgmiim1_pins: rgmiim1-pins {
75			rockchip,pins =
76				/* rgmii_mdc_m1 */
77				<2 RK_PC2 2 &pcfg_pull_none>,
78				/* rgmii_mdio_m1 */
79				<2 RK_PC1 2 &pcfg_pull_none>,
80				/* rgmii_rxclk_m1 */
81				<2 RK_PD3 2 &pcfg_pull_none>,
82				/* rgmii_rxd0_m1 */
83				<2 RK_PB5 2 &pcfg_pull_none>,
84				/* rgmii_rxd1_m1 */
85				<2 RK_PB6 2 &pcfg_pull_none>,
86				/* rgmii_rxd2_m1 */
87				<2 RK_PC7 2 &pcfg_pull_none>,
88				/* rgmii_rxd3_m1 */
89				<2 RK_PD0 2 &pcfg_pull_none>,
90				/* rgmii_rxdv_m1 */
91				<2 RK_PB4 2 &pcfg_pull_none>,
92				/* rgmii_txclk_m1 */
93				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
94				/* rgmii_txd0_m1 */
95				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
96				/* rgmii_txd1_m1 */
97				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
98				/* rgmii_txd2_m1 */
99				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
100				/* rgmii_txd3_m1 */
101				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
102				/* rgmii_txen_m1 */
103				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
104		};
105	};
106	sdmmc0 {
107		/omit-if-no-ref/
108		sdmmc0_bus4: sdmmc0-bus4 {
109			rockchip,pins =
110				/* sdmmc0_d0 */
111				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
112				/* sdmmc0_d1 */
113				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
114				/* sdmmc0_d2 */
115				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
116				/* sdmmc0_d3 */
117				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
118		};
119		/omit-if-no-ref/
120		sdmmc0_clk: sdmmc0-clk {
121			rockchip,pins =
122				/* sdmmc0_clk */
123				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
124		};
125		/omit-if-no-ref/
126		sdmmc0_cmd: sdmmc0-cmd {
127			rockchip,pins =
128				/* sdmmc0_cmd */
129				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
130		};
131		/omit-if-no-ref/
132		sdmmc0_det: sdmmc0-det {
133			rockchip,pins =
134				<0 RK_PA3 1 &pcfg_pull_none>;
135		};
136		/omit-if-no-ref/
137		sdmmc0_pwr: sdmmc0-pwr {
138			rockchip,pins =
139				<0 RK_PC0 1 &pcfg_pull_none>;
140		};
141	};
142	sdmmc1 {
143		/omit-if-no-ref/
144		sdmmc1_bus4: sdmmc1-bus4 {
145			rockchip,pins =
146				/* sdmmc1_d0 */
147				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
148				/* sdmmc1_d1 */
149				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
150				/* sdmmc1_d2 */
151				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
152				/* sdmmc1_d3 */
153				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
154		};
155		/omit-if-no-ref/
156		sdmmc1_clk: sdmmc1-clk {
157			rockchip,pins =
158				/* sdmmc1_clk */
159				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
160		};
161		/omit-if-no-ref/
162		sdmmc1_cmd: sdmmc1-cmd {
163			rockchip,pins =
164				/* sdmmc1_cmd */
165				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
166		};
167		/omit-if-no-ref/
168		sdmmc1_det: sdmmc1-det {
169			rockchip,pins =
170				<1 RK_PD0 2 &pcfg_pull_none>;
171		};
172		/omit-if-no-ref/
173		sdmmc1_pwr: sdmmc1-pwr {
174			rockchip,pins =
175				<1 RK_PD1 2 &pcfg_pull_none>;
176		};
177	};
178	uart0 {
179		/omit-if-no-ref/
180		uart0_xfer: uart0-xfer {
181			rockchip,pins =
182				/* uart0_rx */
183				<1 RK_PC2 1 &pcfg_pull_up>,
184				/* uart0_tx */
185				<1 RK_PC3 1 &pcfg_pull_up>;
186		};
187		/omit-if-no-ref/
188		uart0_ctsn: uart0-ctsn {
189			rockchip,pins =
190				<1 RK_PC1 1 &pcfg_pull_none>;
191		};
192		/omit-if-no-ref/
193		uart0_rtsn: uart0-rtsn {
194			rockchip,pins =
195				<1 RK_PC0 1 &pcfg_pull_none>;
196		};
197		/omit-if-no-ref/
198		uart0_rtsn_gpio: uart0-rts-pin {
199			rockchip,pins =
200				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
201		};
202	};
203	uart1 {
204		/omit-if-no-ref/
205		uart1m0_xfer: uart1m0-xfer {
206			rockchip,pins =
207				/* uart1_rx_m0 */
208				<0 RK_PB7 2 &pcfg_pull_up>,
209				/* uart1_tx_m0 */
210				<0 RK_PB6 2 &pcfg_pull_up>;
211		};
212	};
213	uart2 {
214		/omit-if-no-ref/
215		uart2m1_xfer: uart2m1-xfer {
216			rockchip,pins =
217				/* uart2_rx_m1 */
218				<3 RK_PA3 1 &pcfg_pull_up>,
219				/* uart2_tx_m1 */
220				<3 RK_PA2 1 &pcfg_pull_up>;
221		};
222	};
223	uart3 {
224		/omit-if-no-ref/
225		uart3m0_xfer: uart3m0-xfer {
226			rockchip,pins =
227				/* uart3_rx_m0 */
228				<3 RK_PC7 4 &pcfg_pull_up>,
229				/* uart3_tx_m0 */
230				<3 RK_PC6 4 &pcfg_pull_up>;
231		};
232	};
233	uart4 {
234		/omit-if-no-ref/
235		uart4m0_xfer: uart4m0-xfer {
236			rockchip,pins =
237				/* uart4_rx_m0 */
238				<3 RK_PA5 4 &pcfg_pull_up>,
239				/* uart4_tx_m0 */
240				<3 RK_PA4 4 &pcfg_pull_up>;
241		};
242	};
243	uart5 {
244		/omit-if-no-ref/
245		uart5m0_xfer: uart5m0-xfer {
246			rockchip,pins =
247				/* uart5_rx_m0 */
248				<3 RK_PA7 4 &pcfg_pull_up>,
249				/* uart5_tx_m0 */
250				<3 RK_PA6 4 &pcfg_pull_up>;
251		};
252	};
253};
254