1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "armv7-m.dtsi"
44#include <dt-bindings/clock/stm32fx-clock.h>
45#include <dt-bindings/mfd/stm32f7-rcc.h>
46
47/ {
48	#address-cells = <1>;
49	#size-cells = <1>;
50
51	clocks {
52		clk_hse: clk-hse {
53			#clock-cells = <0>;
54			compatible = "fixed-clock";
55			clock-frequency = <0>;
56		};
57
58		clk-lse {
59			#clock-cells = <0>;
60			compatible = "fixed-clock";
61			clock-frequency = <32768>;
62		};
63
64		clk-lsi {
65			#clock-cells = <0>;
66			compatible = "fixed-clock";
67			clock-frequency = <32000>;
68		};
69
70		clk_i2s_ckin: clk-i2s-ckin {
71			#clock-cells = <0>;
72			compatible = "fixed-clock";
73			clock-frequency = <48000000>;
74		};
75	};
76
77	soc {
78		timers2: timers@40000000 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			compatible = "st,stm32-timers";
82			reg = <0x40000000 0x400>;
83			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
84			clock-names = "int";
85			status = "disabled";
86
87			pwm {
88				compatible = "st,stm32-pwm";
89				#pwm-cells = <3>;
90				status = "disabled";
91			};
92
93			timer@1 {
94				compatible = "st,stm32-timer-trigger";
95				reg = <1>;
96				status = "disabled";
97			};
98		};
99
100		timers3: timers@40000400 {
101			#address-cells = <1>;
102			#size-cells = <0>;
103			compatible = "st,stm32-timers";
104			reg = <0x40000400 0x400>;
105			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
106			clock-names = "int";
107			status = "disabled";
108
109			pwm {
110				compatible = "st,stm32-pwm";
111				#pwm-cells = <3>;
112				status = "disabled";
113			};
114
115			timer@2 {
116				compatible = "st,stm32-timer-trigger";
117				reg = <2>;
118				status = "disabled";
119			};
120		};
121
122		timers4: timers@40000800 {
123			#address-cells = <1>;
124			#size-cells = <0>;
125			compatible = "st,stm32-timers";
126			reg = <0x40000800 0x400>;
127			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
128			clock-names = "int";
129			status = "disabled";
130
131			pwm {
132				compatible = "st,stm32-pwm";
133				#pwm-cells = <3>;
134				status = "disabled";
135			};
136
137			timer@3 {
138				compatible = "st,stm32-timer-trigger";
139				reg = <3>;
140				status = "disabled";
141			};
142		};
143
144		timers5: timers@40000c00 {
145			#address-cells = <1>;
146			#size-cells = <0>;
147			compatible = "st,stm32-timers";
148			reg = <0x40000C00 0x400>;
149			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
150			clock-names = "int";
151			status = "disabled";
152
153			pwm {
154				compatible = "st,stm32-pwm";
155				#pwm-cells = <3>;
156				status = "disabled";
157			};
158
159			timer@4 {
160				compatible = "st,stm32-timer-trigger";
161				reg = <4>;
162				status = "disabled";
163			};
164		};
165
166		timers6: timers@40001000 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			compatible = "st,stm32-timers";
170			reg = <0x40001000 0x400>;
171			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
172			clock-names = "int";
173			status = "disabled";
174
175			timer@5 {
176				compatible = "st,stm32-timer-trigger";
177				reg = <5>;
178				status = "disabled";
179			};
180		};
181
182		timers7: timers@40001400 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			compatible = "st,stm32-timers";
186			reg = <0x40001400 0x400>;
187			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
188			clock-names = "int";
189			status = "disabled";
190
191			timer@6 {
192				compatible = "st,stm32-timer-trigger";
193				reg = <6>;
194				status = "disabled";
195			};
196		};
197
198		timers12: timers@40001800 {
199			#address-cells = <1>;
200			#size-cells = <0>;
201			compatible = "st,stm32-timers";
202			reg = <0x40001800 0x400>;
203			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
204			clock-names = "int";
205			status = "disabled";
206
207			pwm {
208				compatible = "st,stm32-pwm";
209				#pwm-cells = <3>;
210				status = "disabled";
211			};
212
213			timer@11 {
214				compatible = "st,stm32-timer-trigger";
215				reg = <11>;
216				status = "disabled";
217			};
218		};
219
220		timers13: timers@40001c00 {
221			compatible = "st,stm32-timers";
222			reg = <0x40001C00 0x400>;
223			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
224			clock-names = "int";
225			status = "disabled";
226
227			pwm {
228				compatible = "st,stm32-pwm";
229				#pwm-cells = <3>;
230				status = "disabled";
231			};
232		};
233
234		timers14: timers@40002000 {
235			compatible = "st,stm32-timers";
236			reg = <0x40002000 0x400>;
237			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
238			clock-names = "int";
239			status = "disabled";
240
241			pwm {
242				compatible = "st,stm32-pwm";
243				#pwm-cells = <3>;
244				status = "disabled";
245			};
246		};
247
248		rtc: rtc@40002800 {
249			compatible = "st,stm32-rtc";
250			reg = <0x40002800 0x400>;
251			clocks = <&rcc 1 CLK_RTC>;
252			assigned-clocks = <&rcc 1 CLK_RTC>;
253			assigned-clock-parents = <&rcc 1 CLK_LSE>;
254			interrupt-parent = <&exti>;
255			interrupts = <17 1>;
256			st,syscfg = <&pwrcfg 0x00 0x100>;
257			status = "disabled";
258		};
259
260		usart2: serial@40004400 {
261			compatible = "st,stm32f7-uart";
262			reg = <0x40004400 0x400>;
263			interrupts = <38>;
264			clocks = <&rcc 1 CLK_USART2>;
265			status = "disabled";
266		};
267
268		usart3: serial@40004800 {
269			compatible = "st,stm32f7-uart";
270			reg = <0x40004800 0x400>;
271			interrupts = <39>;
272			clocks = <&rcc 1 CLK_USART3>;
273			status = "disabled";
274		};
275
276		usart4: serial@40004c00 {
277			compatible = "st,stm32f7-uart";
278			reg = <0x40004c00 0x400>;
279			interrupts = <52>;
280			clocks = <&rcc 1 CLK_UART4>;
281			status = "disabled";
282		};
283
284		usart5: serial@40005000 {
285			compatible = "st,stm32f7-uart";
286			reg = <0x40005000 0x400>;
287			interrupts = <53>;
288			clocks = <&rcc 1 CLK_UART5>;
289			status = "disabled";
290		};
291
292		i2c1: i2c@40005400 {
293			compatible = "st,stm32f7-i2c";
294			reg = <0x40005400 0x400>;
295			interrupts = <31>,
296				     <32>;
297			resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
298			clocks = <&rcc 1 CLK_I2C1>;
299			#address-cells = <1>;
300			#size-cells = <0>;
301			status = "disabled";
302		};
303
304		i2c2: i2c@40005800 {
305			compatible = "st,stm32f7-i2c";
306			reg = <0x40005800 0x400>;
307			interrupts = <33>,
308				     <34>;
309			resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
310			clocks = <&rcc 1 CLK_I2C2>;
311			#address-cells = <1>;
312			#size-cells = <0>;
313			status = "disabled";
314		};
315
316		i2c3: i2c@40005c00 {
317			compatible = "st,stm32f7-i2c";
318			reg = <0x40005c00 0x400>;
319			interrupts = <72>,
320				     <73>;
321			resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
322			clocks = <&rcc 1 CLK_I2C3>;
323			#address-cells = <1>;
324			#size-cells = <0>;
325			status = "disabled";
326		};
327
328		i2c4: i2c@40006000 {
329			compatible = "st,stm32f7-i2c";
330			reg = <0x40006000 0x400>;
331			interrupts = <95>,
332				     <96>;
333			resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
334			clocks = <&rcc 1 CLK_I2C4>;
335			#address-cells = <1>;
336			#size-cells = <0>;
337			status = "disabled";
338		};
339
340		cec: cec@40006c00 {
341			compatible = "st,stm32-cec";
342			reg = <0x40006C00 0x400>;
343			interrupts = <94>;
344			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
345			clock-names = "cec", "hdmi-cec";
346			status = "disabled";
347		};
348
349		usart7: serial@40007800 {
350			compatible = "st,stm32f7-uart";
351			reg = <0x40007800 0x400>;
352			interrupts = <82>;
353			clocks = <&rcc 1 CLK_UART7>;
354			status = "disabled";
355		};
356
357		usart8: serial@40007c00 {
358			compatible = "st,stm32f7-uart";
359			reg = <0x40007c00 0x400>;
360			interrupts = <83>;
361			clocks = <&rcc 1 CLK_UART8>;
362			status = "disabled";
363		};
364
365		timers1: timers@40010000 {
366			#address-cells = <1>;
367			#size-cells = <0>;
368			compatible = "st,stm32-timers";
369			reg = <0x40010000 0x400>;
370			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
371			clock-names = "int";
372			status = "disabled";
373
374			pwm {
375				compatible = "st,stm32-pwm";
376				#pwm-cells = <3>;
377				status = "disabled";
378			};
379
380			timer@0 {
381				compatible = "st,stm32-timer-trigger";
382				reg = <0>;
383				status = "disabled";
384			};
385		};
386
387		timers8: timers@40010400 {
388			#address-cells = <1>;
389			#size-cells = <0>;
390			compatible = "st,stm32-timers";
391			reg = <0x40010400 0x400>;
392			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
393			clock-names = "int";
394			status = "disabled";
395
396			pwm {
397				compatible = "st,stm32-pwm";
398				#pwm-cells = <3>;
399				status = "disabled";
400			};
401
402			timer@7 {
403				compatible = "st,stm32-timer-trigger";
404				reg = <7>;
405				status = "disabled";
406			};
407		};
408
409		usart1: serial@40011000 {
410			compatible = "st,stm32f7-uart";
411			reg = <0x40011000 0x400>;
412			interrupts = <37>;
413			clocks = <&rcc 1 CLK_USART1>;
414			status = "disabled";
415		};
416
417		usart6: serial@40011400 {
418			compatible = "st,stm32f7-uart";
419			reg = <0x40011400 0x400>;
420			interrupts = <71>;
421			clocks = <&rcc 1 CLK_USART6>;
422			status = "disabled";
423		};
424
425		sdio2: mmc@40011c00 {
426			compatible = "arm,pl180", "arm,primecell";
427			arm,primecell-periphid = <0x00880180>;
428			reg = <0x40011c00 0x400>;
429			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
430			clock-names = "apb_pclk";
431			interrupts = <103>;
432			max-frequency = <48000000>;
433			status = "disabled";
434		};
435
436		sdio1: mmc@40012c00 {
437			compatible = "arm,pl180", "arm,primecell";
438			arm,primecell-periphid = <0x00880180>;
439			reg = <0x40012c00 0x400>;
440			clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
441			clock-names = "apb_pclk";
442			interrupts = <49>;
443			max-frequency = <48000000>;
444			status = "disabled";
445		};
446
447		syscfg: syscon@40013800 {
448			compatible = "st,stm32-syscfg", "syscon";
449			reg = <0x40013800 0x400>;
450		};
451
452		exti: interrupt-controller@40013c00 {
453			compatible = "st,stm32-exti";
454			interrupt-controller;
455			#interrupt-cells = <2>;
456			reg = <0x40013C00 0x400>;
457			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
458		};
459
460		timers9: timers@40014000 {
461			#address-cells = <1>;
462			#size-cells = <0>;
463			compatible = "st,stm32-timers";
464			reg = <0x40014000 0x400>;
465			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
466			clock-names = "int";
467			status = "disabled";
468
469			pwm {
470				compatible = "st,stm32-pwm";
471				#pwm-cells = <3>;
472				status = "disabled";
473			};
474
475			timer@8 {
476				compatible = "st,stm32-timer-trigger";
477				reg = <8>;
478				status = "disabled";
479			};
480		};
481
482		timers10: timers@40014400 {
483			compatible = "st,stm32-timers";
484			reg = <0x40014400 0x400>;
485			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
486			clock-names = "int";
487			status = "disabled";
488
489			pwm {
490				compatible = "st,stm32-pwm";
491				#pwm-cells = <3>;
492				status = "disabled";
493			};
494		};
495
496		timers11: timers@40014800 {
497			compatible = "st,stm32-timers";
498			reg = <0x40014800 0x400>;
499			clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
500			clock-names = "int";
501			status = "disabled";
502
503			pwm {
504				compatible = "st,stm32-pwm";
505				#pwm-cells = <3>;
506				status = "disabled";
507			};
508		};
509
510		pwrcfg: power-config@40007000 {
511			compatible = "st,stm32-power-config", "syscon";
512			reg = <0x40007000 0x400>;
513		};
514
515		crc: crc@40023000 {
516			compatible = "st,stm32f7-crc";
517			reg = <0x40023000 0x400>;
518			clocks = <&rcc 0 12>;
519			status = "disabled";
520		};
521
522		rcc: rcc@40023800 {
523			#reset-cells = <1>;
524			#clock-cells = <2>;
525			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
526			reg = <0x40023800 0x400>;
527			clocks = <&clk_hse>, <&clk_i2s_ckin>;
528			st,syscfg = <&pwrcfg>;
529			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
530			assigned-clock-rates = <1000000>;
531		};
532
533		dma1: dma-controller@40026000 {
534			compatible = "st,stm32-dma";
535			reg = <0x40026000 0x400>;
536			interrupts = <11>,
537				     <12>,
538				     <13>,
539				     <14>,
540				     <15>,
541				     <16>,
542				     <17>,
543				     <47>;
544			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
545			#dma-cells = <4>;
546			status = "disabled";
547		};
548
549		dma2: dma-controller@40026400 {
550			compatible = "st,stm32-dma";
551			reg = <0x40026400 0x400>;
552			interrupts = <56>,
553				     <57>,
554				     <58>,
555				     <59>,
556				     <60>,
557				     <68>,
558				     <69>,
559				     <70>;
560			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
561			#dma-cells = <4>;
562			st,mem2mem;
563			status = "disabled";
564		};
565
566		usbotg_hs: usb@40040000 {
567			compatible = "st,stm32f7-hsotg";
568			reg = <0x40040000 0x40000>;
569			interrupts = <77>;
570			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
571			clock-names = "otg";
572			g-rx-fifo-size = <256>;
573			g-np-tx-fifo-size = <32>;
574			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
575			status = "disabled";
576		};
577
578		usbotg_fs: usb@50000000 {
579			compatible = "st,stm32f4x9-fsotg";
580			reg = <0x50000000 0x40000>;
581			interrupts = <67>;
582			clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
583			clock-names = "otg";
584			status = "disabled";
585		};
586	};
587};
588
589&systick {
590	clocks = <&rcc 1 0>;
591	status = "okay";
592};
593