1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	arm-pmu {
26		compatible = "arm,cortex-a7-pmu";
27		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28		interrupt-affinity = <&cpu0>;
29		interrupt-parent = <&intc>;
30	};
31
32	firmware {
33		optee {
34			method = "smc";
35			compatible = "linaro,optee-tz";
36		};
37
38		scmi: scmi {
39			compatible = "linaro,scmi-optee";
40			#address-cells = <1>;
41			#size-cells = <0>;
42			linaro,optee-channel-id = <0>;
43			shmem = <&scmi_shm>;
44
45			scmi_clk: protocol@14 {
46				reg = <0x14>;
47				#clock-cells = <1>;
48			};
49
50			scmi_reset: protocol@16 {
51				reg = <0x16>;
52				#reset-cells = <1>;
53			};
54		};
55	};
56
57	intc: interrupt-controller@a0021000 {
58		compatible = "arm,cortex-a7-gic";
59		#interrupt-cells = <3>;
60		interrupt-controller;
61		reg = <0xa0021000 0x1000>,
62		      <0xa0022000 0x2000>;
63	};
64
65	psci {
66		compatible = "arm,psci-1.0";
67		method = "smc";
68	};
69
70	timer {
71		compatible = "arm,armv7-timer";
72		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
73			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
76		interrupt-parent = <&intc>;
77		always-on;
78	};
79
80	/* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
81	reg11: reg11 {
82		compatible = "regulator-fixed";
83		regulator-name = "reg11";
84		regulator-min-microvolt = <1100000>;
85		regulator-max-microvolt = <1100000>;
86	};
87
88	reg18: reg18 {
89		compatible = "regulator-fixed";
90		regulator-name = "reg18";
91		regulator-min-microvolt = <1800000>;
92		regulator-max-microvolt = <1800000>;
93	};
94
95	usb33: usb33 {
96		compatible = "regulator-fixed";
97		regulator-name = "usb33";
98		regulator-min-microvolt = <3300000>;
99		regulator-max-microvolt = <3300000>;
100	};
101
102	soc {
103		compatible = "simple-bus";
104		#address-cells = <1>;
105		#size-cells = <1>;
106		interrupt-parent = <&intc>;
107		ranges;
108
109		scmi_sram: sram@2ffff000 {
110			compatible = "mmio-sram";
111			reg = <0x2ffff000 0x1000>;
112			#address-cells = <1>;
113			#size-cells = <1>;
114			ranges = <0 0x2ffff000 0x1000>;
115
116			scmi_shm: scmi-sram@0 {
117				compatible = "arm,scmi-shmem";
118				reg = <0 0x80>;
119			};
120		};
121
122		timers2: timer@40000000 {
123			#address-cells = <1>;
124			#size-cells = <0>;
125			compatible = "st,stm32-timers";
126			reg = <0x40000000 0x400>;
127			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
128			interrupt-names = "global";
129			clocks = <&rcc TIM2_K>;
130			clock-names = "int";
131			dmas = <&dmamux1 18 0x400 0x1>,
132			       <&dmamux1 19 0x400 0x1>,
133			       <&dmamux1 20 0x400 0x1>,
134			       <&dmamux1 21 0x400 0x1>,
135			       <&dmamux1 22 0x400 0x1>;
136			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
137			status = "disabled";
138
139			pwm {
140				compatible = "st,stm32-pwm";
141				#pwm-cells = <3>;
142				status = "disabled";
143			};
144
145			timer@1 {
146				compatible = "st,stm32h7-timer-trigger";
147				reg = <1>;
148				status = "disabled";
149			};
150
151			counter {
152				compatible = "st,stm32-timer-counter";
153				status = "disabled";
154			};
155		};
156
157		timers3: timer@40001000 {
158			#address-cells = <1>;
159			#size-cells = <0>;
160			compatible = "st,stm32-timers";
161			reg = <0x40001000 0x400>;
162			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
163			interrupt-names = "global";
164			clocks = <&rcc TIM3_K>;
165			clock-names = "int";
166			dmas = <&dmamux1 23 0x400 0x1>,
167			       <&dmamux1 24 0x400 0x1>,
168			       <&dmamux1 25 0x400 0x1>,
169			       <&dmamux1 26 0x400 0x1>,
170			       <&dmamux1 27 0x400 0x1>,
171			       <&dmamux1 28 0x400 0x1>;
172			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
173			status = "disabled";
174
175			pwm {
176				compatible = "st,stm32-pwm";
177				#pwm-cells = <3>;
178				status = "disabled";
179			};
180
181			timer@2 {
182				compatible = "st,stm32h7-timer-trigger";
183				reg = <2>;
184				status = "disabled";
185			};
186
187			counter {
188				compatible = "st,stm32-timer-counter";
189				status = "disabled";
190			};
191		};
192
193		timers4: timer@40002000 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "st,stm32-timers";
197			reg = <0x40002000 0x400>;
198			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
199			interrupt-names = "global";
200			clocks = <&rcc TIM4_K>;
201			clock-names = "int";
202			dmas = <&dmamux1 29 0x400 0x1>,
203			       <&dmamux1 30 0x400 0x1>,
204			       <&dmamux1 31 0x400 0x1>,
205			       <&dmamux1 32 0x400 0x1>;
206			dma-names = "ch1", "ch2", "ch3", "up";
207			status = "disabled";
208
209			pwm {
210				compatible = "st,stm32-pwm";
211				#pwm-cells = <3>;
212				status = "disabled";
213			};
214
215			timer@3 {
216				compatible = "st,stm32h7-timer-trigger";
217				reg = <3>;
218				status = "disabled";
219			};
220
221			counter {
222				compatible = "st,stm32-timer-counter";
223				status = "disabled";
224			};
225		};
226
227		timers5: timer@40003000 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			compatible = "st,stm32-timers";
231			reg = <0x40003000 0x400>;
232			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
233			interrupt-names = "global";
234			clocks = <&rcc TIM5_K>;
235			clock-names = "int";
236			dmas = <&dmamux1 55 0x400 0x1>,
237			       <&dmamux1 56 0x400 0x1>,
238			       <&dmamux1 57 0x400 0x1>,
239			       <&dmamux1 58 0x400 0x1>,
240			       <&dmamux1 59 0x400 0x1>,
241			       <&dmamux1 60 0x400 0x1>;
242			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
243			status = "disabled";
244
245			pwm {
246				compatible = "st,stm32-pwm";
247				#pwm-cells = <3>;
248				status = "disabled";
249			};
250
251			timer@4 {
252				compatible = "st,stm32h7-timer-trigger";
253				reg = <4>;
254				status = "disabled";
255			};
256
257			counter {
258				compatible = "st,stm32-timer-counter";
259				status = "disabled";
260			};
261		};
262
263		timers6: timer@40004000 {
264			#address-cells = <1>;
265			#size-cells = <0>;
266			compatible = "st,stm32-timers";
267			reg = <0x40004000 0x400>;
268			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
269			interrupt-names = "global";
270			clocks = <&rcc TIM6_K>;
271			clock-names = "int";
272			dmas = <&dmamux1 69 0x400 0x1>;
273			dma-names = "up";
274			status = "disabled";
275
276			timer@5 {
277				compatible = "st,stm32h7-timer-trigger";
278				reg = <5>;
279				status = "disabled";
280			};
281		};
282
283		timers7: timer@40005000 {
284			#address-cells = <1>;
285			#size-cells = <0>;
286			compatible = "st,stm32-timers";
287			reg = <0x40005000 0x400>;
288			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
289			interrupt-names = "global";
290			clocks = <&rcc TIM7_K>;
291			clock-names = "int";
292			dmas = <&dmamux1 70 0x400 0x1>;
293			dma-names = "up";
294			status = "disabled";
295
296			timer@6 {
297				compatible = "st,stm32h7-timer-trigger";
298				reg = <6>;
299				status = "disabled";
300			};
301		};
302
303		lptimer1: timer@40009000 {
304			#address-cells = <1>;
305			#size-cells = <0>;
306			compatible = "st,stm32-lptimer";
307			reg = <0x40009000 0x400>;
308			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
309			clocks = <&rcc LPTIM1_K>;
310			clock-names = "mux";
311			wakeup-source;
312			status = "disabled";
313
314			pwm {
315				compatible = "st,stm32-pwm-lp";
316				#pwm-cells = <3>;
317				status = "disabled";
318			};
319
320			trigger@0 {
321				compatible = "st,stm32-lptimer-trigger";
322				reg = <0>;
323				status = "disabled";
324			};
325
326			counter {
327				compatible = "st,stm32-lptimer-counter";
328				status = "disabled";
329			};
330
331			timer {
332				compatible = "st,stm32-lptimer-timer";
333				status = "disabled";
334			};
335		};
336
337		i2s2: audio-controller@4000b000 {
338			compatible = "st,stm32h7-i2s";
339			reg = <0x4000b000 0x400>;
340			#sound-dai-cells = <0>;
341			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
342			dmas = <&dmamux1 39 0x400 0x01>,
343			       <&dmamux1 40 0x400 0x01>;
344			dma-names = "rx", "tx";
345			status = "disabled";
346		};
347
348		spi2: spi@4000b000 {
349			compatible = "st,stm32h7-spi";
350			reg = <0x4000b000 0x400>;
351			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
352			clocks = <&rcc SPI2_K>;
353			resets = <&rcc SPI2_R>;
354			#address-cells = <1>;
355			#size-cells = <0>;
356			dmas = <&dmamux1 39 0x400 0x01>,
357			       <&dmamux1 40 0x400 0x01>;
358			dma-names = "rx", "tx";
359			status = "disabled";
360		};
361
362		i2s3: audio-controller@4000c000 {
363			compatible = "st,stm32h7-i2s";
364			reg = <0x4000c000 0x400>;
365			#sound-dai-cells = <0>;
366			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
367			dmas = <&dmamux1 61 0x400 0x01>,
368			       <&dmamux1 62 0x400 0x01>;
369			dma-names = "rx", "tx";
370			status = "disabled";
371		};
372
373		spi3: spi@4000c000 {
374			compatible = "st,stm32h7-spi";
375			reg = <0x4000c000 0x400>;
376			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
377			clocks = <&rcc SPI3_K>;
378			resets = <&rcc SPI3_R>;
379			#address-cells = <1>;
380			#size-cells = <0>;
381			dmas = <&dmamux1 61 0x400 0x01>,
382			       <&dmamux1 62 0x400 0x01>;
383			dma-names = "rx", "tx";
384			status = "disabled";
385		};
386
387		spdifrx: audio-controller@4000d000 {
388			compatible = "st,stm32h7-spdifrx";
389			reg = <0x4000d000 0x400>;
390			#sound-dai-cells = <0>;
391			clocks = <&rcc SPDIF_K>;
392			clock-names = "kclk";
393			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
394			dmas = <&dmamux1 93 0x400 0x01>,
395			       <&dmamux1 94 0x400 0x01>;
396			dma-names = "rx", "rx-ctrl";
397			status = "disabled";
398		};
399
400		uart4: serial@40010000 {
401			compatible = "st,stm32h7-uart";
402			reg = <0x40010000 0x400>;
403			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
404			clocks = <&rcc UART4_K>;
405			resets = <&rcc UART4_R>;
406			status = "disabled";
407		};
408
409		i2c1: i2c@40012000 {
410			compatible = "st,stm32mp13-i2c";
411			reg = <0x40012000 0x400>;
412			interrupt-names = "event", "error";
413			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
414				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
415			clocks = <&rcc I2C1_K>;
416			resets = <&rcc I2C1_R>;
417			#address-cells = <1>;
418			#size-cells = <0>;
419			dmas = <&dmamux1 33 0x400 0x1>,
420			       <&dmamux1 34 0x400 0x1>;
421			dma-names = "rx", "tx";
422			st,syscfg-fmp = <&syscfg 0x4 0x1>;
423			i2c-analog-filter;
424			status = "disabled";
425		};
426
427		i2c2: i2c@40013000 {
428			compatible = "st,stm32mp13-i2c";
429			reg = <0x40013000 0x400>;
430			interrupt-names = "event", "error";
431			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
432				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
433			clocks = <&rcc I2C2_K>;
434			resets = <&rcc I2C2_R>;
435			#address-cells = <1>;
436			#size-cells = <0>;
437			dmas = <&dmamux1 35 0x400 0x1>,
438			       <&dmamux1 36 0x400 0x1>;
439			dma-names = "rx", "tx";
440			st,syscfg-fmp = <&syscfg 0x4 0x2>;
441			i2c-analog-filter;
442			status = "disabled";
443		};
444
445		timers1: timer@44000000 {
446			#address-cells = <1>;
447			#size-cells = <0>;
448			compatible = "st,stm32-timers";
449			reg = <0x44000000 0x400>;
450			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
451				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
452				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
453				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
454			interrupt-names = "brk", "up", "trg-com", "cc";
455			clocks = <&rcc TIM1_K>;
456			clock-names = "int";
457			dmas = <&dmamux1 11 0x400 0x1>,
458			       <&dmamux1 12 0x400 0x1>,
459			       <&dmamux1 13 0x400 0x1>,
460			       <&dmamux1 14 0x400 0x1>,
461			       <&dmamux1 15 0x400 0x1>,
462			       <&dmamux1 16 0x400 0x1>,
463			       <&dmamux1 17 0x400 0x1>;
464			dma-names = "ch1", "ch2", "ch3", "ch4",
465				    "up", "trig", "com";
466			status = "disabled";
467
468			pwm {
469				compatible = "st,stm32-pwm";
470				#pwm-cells = <3>;
471				status = "disabled";
472			};
473
474			timer@0 {
475				compatible = "st,stm32h7-timer-trigger";
476				reg = <0>;
477				status = "disabled";
478			};
479
480			counter {
481				compatible = "st,stm32-timer-counter";
482				status = "disabled";
483			};
484		};
485
486		timers8: timer@44001000 {
487			#address-cells = <1>;
488			#size-cells = <0>;
489			compatible = "st,stm32-timers";
490			reg = <0x44001000 0x400>;
491			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
492				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
493				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
494				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
495			interrupt-names = "brk", "up", "trg-com", "cc";
496			clocks = <&rcc TIM8_K>;
497			clock-names = "int";
498			dmas = <&dmamux1 47 0x400 0x1>,
499			       <&dmamux1 48 0x400 0x1>,
500			       <&dmamux1 49 0x400 0x1>,
501			       <&dmamux1 50 0x400 0x1>,
502			       <&dmamux1 51 0x400 0x1>,
503			       <&dmamux1 52 0x400 0x1>,
504			       <&dmamux1 53 0x400 0x1>;
505			dma-names = "ch1", "ch2", "ch3", "ch4",
506				    "up", "trig", "com";
507			status = "disabled";
508
509			pwm {
510				compatible = "st,stm32-pwm";
511				#pwm-cells = <3>;
512				status = "disabled";
513			};
514
515			timer@7 {
516				compatible = "st,stm32h7-timer-trigger";
517				reg = <7>;
518				status = "disabled";
519			};
520
521			counter {
522				compatible = "st,stm32-timer-counter";
523				status = "disabled";
524			};
525		};
526
527		i2s1: audio-controller@44004000 {
528			compatible = "st,stm32h7-i2s";
529			reg = <0x44004000 0x400>;
530			#sound-dai-cells = <0>;
531			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
532			dmas = <&dmamux1 37 0x400 0x01>,
533			       <&dmamux1 38 0x400 0x01>;
534			dma-names = "rx", "tx";
535			status = "disabled";
536		};
537
538		spi1: spi@44004000 {
539			compatible = "st,stm32h7-spi";
540			reg = <0x44004000 0x400>;
541			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
542			clocks = <&rcc SPI1_K>;
543			resets = <&rcc SPI1_R>;
544			#address-cells = <1>;
545			#size-cells = <0>;
546			dmas = <&dmamux1 37 0x400 0x01>,
547			       <&dmamux1 38 0x400 0x01>;
548			dma-names = "rx", "tx";
549			status = "disabled";
550		};
551
552		sai1: sai@4400a000 {
553			compatible = "st,stm32h7-sai";
554			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
555			ranges = <0 0x4400a000 0x400>;
556			#address-cells = <1>;
557			#size-cells = <1>;
558			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
559			resets = <&rcc SAI1_R>;
560			status = "disabled";
561
562			sai1a: audio-controller@4400a004 {
563				compatible = "st,stm32-sai-sub-a";
564				reg = <0x4 0x20>;
565				#sound-dai-cells = <0>;
566				clocks = <&rcc SAI1_K>;
567				clock-names = "sai_ck";
568				dmas = <&dmamux1 87 0x400 0x01>;
569				status = "disabled";
570			};
571
572			sai1b: audio-controller@4400a024 {
573				compatible = "st,stm32-sai-sub-b";
574				reg = <0x24 0x20>;
575				#sound-dai-cells = <0>;
576				clocks = <&rcc SAI1_K>;
577				clock-names = "sai_ck";
578				dmas = <&dmamux1 88 0x400 0x01>;
579				status = "disabled";
580			};
581		};
582
583		sai2: sai@4400b000 {
584			compatible = "st,stm32h7-sai";
585			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
586			ranges = <0 0x4400b000 0x400>;
587			#address-cells = <1>;
588			#size-cells = <1>;
589			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
590			resets = <&rcc SAI2_R>;
591			status = "disabled";
592
593			sai2a: audio-controller@4400b004 {
594				compatible = "st,stm32-sai-sub-a";
595				reg = <0x4 0x20>;
596				#sound-dai-cells = <0>;
597				clocks = <&rcc SAI2_K>;
598				clock-names = "sai_ck";
599				dmas = <&dmamux1 89 0x400 0x01>;
600				status = "disabled";
601			};
602
603			sai2b: audio-controller@4400b024 {
604				compatible = "st,stm32-sai-sub-b";
605				reg = <0x24 0x20>;
606				#sound-dai-cells = <0>;
607				clocks = <&rcc SAI2_K>;
608				clock-names = "sai_ck";
609				dmas = <&dmamux1 90 0x400 0x01>;
610				status = "disabled";
611			};
612		};
613
614		dfsdm: dfsdm@4400d000 {
615			compatible = "st,stm32mp1-dfsdm";
616			reg = <0x4400d000 0x800>;
617			clocks = <&rcc DFSDM_K>;
618			clock-names = "dfsdm";
619			#address-cells = <1>;
620			#size-cells = <0>;
621			status = "disabled";
622
623			dfsdm0: filter@0 {
624				compatible = "st,stm32-dfsdm-adc";
625				reg = <0>;
626				#io-channel-cells = <1>;
627				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
628				dmas = <&dmamux1 101 0x400 0x01>;
629				dma-names = "rx";
630				status = "disabled";
631			};
632
633			dfsdm1: filter@1 {
634				compatible = "st,stm32-dfsdm-adc";
635				reg = <1>;
636				#io-channel-cells = <1>;
637				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
638				dmas = <&dmamux1 102 0x400 0x01>;
639				dma-names = "rx";
640				status = "disabled";
641			};
642		};
643
644		dma1: dma-controller@48000000 {
645			compatible = "st,stm32-dma";
646			reg = <0x48000000 0x400>;
647			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
648				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
649				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
650				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
651				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
652				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
653				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
654				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
655			clocks = <&rcc DMA1>;
656			resets = <&rcc DMA1_R>;
657			#dma-cells = <4>;
658			st,mem2mem;
659			dma-requests = <8>;
660		};
661
662		dma2: dma-controller@48001000 {
663			compatible = "st,stm32-dma";
664			reg = <0x48001000 0x400>;
665			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
666				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
667				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
668				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
669				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
670				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
671				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
672				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
673			clocks = <&rcc DMA2>;
674			resets = <&rcc DMA2_R>;
675			#dma-cells = <4>;
676			st,mem2mem;
677			dma-requests = <8>;
678		};
679
680		dmamux1: dma-router@48002000 {
681			compatible = "st,stm32h7-dmamux";
682			reg = <0x48002000 0x40>;
683			clocks = <&rcc DMAMUX1>;
684			resets = <&rcc DMAMUX1_R>;
685			#dma-cells = <3>;
686			dma-masters = <&dma1 &dma2>;
687			dma-requests = <128>;
688			dma-channels = <16>;
689		};
690
691		adc_2: adc@48004000 {
692			compatible = "st,stm32mp13-adc-core";
693			reg = <0x48004000 0x400>;
694			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
695			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
696			clock-names = "bus", "adc";
697			interrupt-controller;
698			#interrupt-cells = <1>;
699			#address-cells = <1>;
700			#size-cells = <0>;
701			status = "disabled";
702
703			adc2: adc@0 {
704				compatible = "st,stm32mp13-adc";
705				#io-channel-cells = <1>;
706				#address-cells = <1>;
707				#size-cells = <0>;
708				reg = <0x0>;
709				interrupt-parent = <&adc_2>;
710				interrupts = <0>;
711				dmas = <&dmamux1 10 0x400 0x80000001>;
712				dma-names = "rx";
713				status = "disabled";
714
715				channel@13 {
716					reg = <13>;
717					label = "vrefint";
718				};
719				channel@14 {
720					reg = <14>;
721					label = "vddcore";
722				};
723				channel@16 {
724					reg = <16>;
725					label = "vddcpu";
726				};
727				channel@17 {
728					reg = <17>;
729					label = "vddq_ddr";
730				};
731			};
732		};
733
734		usbotg_hs: usb@49000000 {
735			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
736			reg = <0x49000000 0x40000>;
737			clocks = <&rcc USBO_K>;
738			clock-names = "otg";
739			resets = <&rcc USBO_R>;
740			reset-names = "dwc2";
741			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
742			g-rx-fifo-size = <512>;
743			g-np-tx-fifo-size = <32>;
744			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
745			dr_mode = "otg";
746			otg-rev = <0x200>;
747			usb33d-supply = <&usb33>;
748			status = "disabled";
749		};
750
751		i2s4: audio-controller@4c002000 {
752			compatible = "st,stm32h7-i2s";
753			reg = <0x4c002000 0x400>;
754			#sound-dai-cells = <0>;
755			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
756			dmas = <&dmamux1 83 0x400 0x01>,
757			       <&dmamux1 84 0x400 0x01>;
758			dma-names = "rx", "tx";
759			status = "disabled";
760		};
761
762		spi4: spi@4c002000 {
763			compatible = "st,stm32h7-spi";
764			reg = <0x4c002000 0x400>;
765			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
766			clocks = <&rcc SPI4_K>;
767			resets = <&rcc SPI4_R>;
768			#address-cells = <1>;
769			#size-cells = <0>;
770			dmas = <&dmamux1 83 0x400 0x01>,
771			       <&dmamux1 84 0x400 0x01>;
772			dma-names = "rx", "tx";
773			status = "disabled";
774		};
775
776		spi5: spi@4c003000 {
777			compatible = "st,stm32h7-spi";
778			reg = <0x4c003000 0x400>;
779			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
780			clocks = <&rcc SPI5_K>;
781			resets = <&rcc SPI5_R>;
782			#address-cells = <1>;
783			#size-cells = <0>;
784			dmas = <&dmamux1 85 0x400 0x01>,
785			       <&dmamux1 86 0x400 0x01>;
786			dma-names = "rx", "tx";
787			status = "disabled";
788		};
789
790		i2c3: i2c@4c004000 {
791			compatible = "st,stm32mp13-i2c";
792			reg = <0x4c004000 0x400>;
793			interrupt-names = "event", "error";
794			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
795				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
796			clocks = <&rcc I2C3_K>;
797			resets = <&rcc I2C3_R>;
798			#address-cells = <1>;
799			#size-cells = <0>;
800			dmas = <&dmamux1 73 0x400 0x1>,
801			       <&dmamux1 74 0x400 0x1>;
802			dma-names = "rx", "tx";
803			st,syscfg-fmp = <&syscfg 0x4 0x4>;
804			i2c-analog-filter;
805			status = "disabled";
806		};
807
808		i2c4: i2c@4c005000 {
809			compatible = "st,stm32mp13-i2c";
810			reg = <0x4c005000 0x400>;
811			interrupt-names = "event", "error";
812			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
813				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
814			clocks = <&rcc I2C4_K>;
815			resets = <&rcc I2C4_R>;
816			#address-cells = <1>;
817			#size-cells = <0>;
818			dmas = <&dmamux1 75 0x400 0x1>,
819			       <&dmamux1 76 0x400 0x1>;
820			dma-names = "rx", "tx";
821			st,syscfg-fmp = <&syscfg 0x4 0x8>;
822			i2c-analog-filter;
823			status = "disabled";
824		};
825
826		i2c5: i2c@4c006000 {
827			compatible = "st,stm32mp13-i2c";
828			reg = <0x4c006000 0x400>;
829			interrupt-names = "event", "error";
830			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
831				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
832			clocks = <&rcc I2C5_K>;
833			resets = <&rcc I2C5_R>;
834			#address-cells = <1>;
835			#size-cells = <0>;
836			dmas = <&dmamux1 115 0x400 0x1>,
837			       <&dmamux1 116 0x400 0x1>;
838			dma-names = "rx", "tx";
839			st,syscfg-fmp = <&syscfg 0x4 0x10>;
840			i2c-analog-filter;
841			status = "disabled";
842		};
843
844		timers12: timer@4c007000 {
845			#address-cells = <1>;
846			#size-cells = <0>;
847			compatible = "st,stm32-timers";
848			reg = <0x4c007000 0x400>;
849			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
850			interrupt-names = "global";
851			clocks = <&rcc TIM12_K>;
852			clock-names = "int";
853			status = "disabled";
854
855			pwm {
856				compatible = "st,stm32-pwm";
857				#pwm-cells = <3>;
858				status = "disabled";
859			};
860
861			timer@11 {
862				compatible = "st,stm32h7-timer-trigger";
863				reg = <11>;
864				status = "disabled";
865			};
866		};
867
868		timers13: timer@4c008000 {
869			#address-cells = <1>;
870			#size-cells = <0>;
871			compatible = "st,stm32-timers";
872			reg = <0x4c008000 0x400>;
873			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
874			interrupt-names = "global";
875			clocks = <&rcc TIM13_K>;
876			clock-names = "int";
877			status = "disabled";
878
879			pwm {
880				compatible = "st,stm32-pwm";
881				#pwm-cells = <3>;
882				status = "disabled";
883			};
884
885			timer@12 {
886				compatible = "st,stm32h7-timer-trigger";
887				reg = <12>;
888				status = "disabled";
889			};
890		};
891
892		timers14: timer@4c009000 {
893			#address-cells = <1>;
894			#size-cells = <0>;
895			compatible = "st,stm32-timers";
896			reg = <0x4c009000 0x400>;
897			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
898			interrupt-names = "global";
899			clocks = <&rcc TIM14_K>;
900			clock-names = "int";
901			status = "disabled";
902
903			pwm {
904				compatible = "st,stm32-pwm";
905				#pwm-cells = <3>;
906				status = "disabled";
907			};
908
909			timer@13 {
910				compatible = "st,stm32h7-timer-trigger";
911				reg = <13>;
912				status = "disabled";
913			};
914		};
915
916		timers15: timer@4c00a000 {
917			#address-cells = <1>;
918			#size-cells = <0>;
919			compatible = "st,stm32-timers";
920			reg = <0x4c00a000 0x400>;
921			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
922			interrupt-names = "global";
923			clocks = <&rcc TIM15_K>;
924			clock-names = "int";
925			dmas = <&dmamux1 105 0x400 0x1>,
926			       <&dmamux1 106 0x400 0x1>,
927			       <&dmamux1 107 0x400 0x1>,
928			       <&dmamux1 108 0x400 0x1>;
929			dma-names = "ch1", "up", "trig", "com";
930			status = "disabled";
931
932			pwm {
933				compatible = "st,stm32-pwm";
934				#pwm-cells = <3>;
935				status = "disabled";
936			};
937
938			timer@14 {
939				compatible = "st,stm32h7-timer-trigger";
940				reg = <14>;
941				status = "disabled";
942			};
943		};
944
945		timers16: timer@4c00b000 {
946			#address-cells = <1>;
947			#size-cells = <0>;
948			compatible = "st,stm32-timers";
949			reg = <0x4c00b000 0x400>;
950			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
951			interrupt-names = "global";
952			clocks = <&rcc TIM16_K>;
953			clock-names = "int";
954			dmas = <&dmamux1 109 0x400 0x1>,
955			       <&dmamux1 110 0x400 0x1>;
956			dma-names = "ch1", "up";
957			status = "disabled";
958
959			pwm {
960				compatible = "st,stm32-pwm";
961				#pwm-cells = <3>;
962				status = "disabled";
963			};
964
965			timer@15 {
966				compatible = "st,stm32h7-timer-trigger";
967				reg = <15>;
968				status = "disabled";
969			};
970		};
971
972		timers17: timer@4c00c000 {
973			#address-cells = <1>;
974			#size-cells = <0>;
975			compatible = "st,stm32-timers";
976			reg = <0x4c00c000 0x400>;
977			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
978			interrupt-names = "global";
979			clocks = <&rcc TIM17_K>;
980			clock-names = "int";
981			dmas = <&dmamux1 111 0x400 0x1>,
982			       <&dmamux1 112 0x400 0x1>;
983			dma-names = "ch1", "up";
984			status = "disabled";
985
986			pwm {
987				compatible = "st,stm32-pwm";
988				#pwm-cells = <3>;
989				status = "disabled";
990			};
991
992			timer@16 {
993				compatible = "st,stm32h7-timer-trigger";
994				reg = <16>;
995				status = "disabled";
996			};
997		};
998
999		rcc: rcc@50000000 {
1000			compatible = "st,stm32mp13-rcc", "syscon";
1001			reg = <0x50000000 0x1000>;
1002			#clock-cells = <1>;
1003			#reset-cells = <1>;
1004			clock-names = "hse", "hsi", "csi", "lse", "lsi";
1005			clocks = <&scmi_clk CK_SCMI_HSE>,
1006				 <&scmi_clk CK_SCMI_HSI>,
1007				 <&scmi_clk CK_SCMI_CSI>,
1008				 <&scmi_clk CK_SCMI_LSE>,
1009				 <&scmi_clk CK_SCMI_LSI>;
1010		};
1011
1012		exti: interrupt-controller@5000d000 {
1013			compatible = "st,stm32mp13-exti", "syscon";
1014			interrupt-controller;
1015			#interrupt-cells = <2>;
1016			reg = <0x5000d000 0x400>;
1017		};
1018
1019		syscfg: syscon@50020000 {
1020			compatible = "st,stm32mp157-syscfg", "syscon";
1021			reg = <0x50020000 0x400>;
1022			clocks = <&rcc SYSCFG>;
1023		};
1024
1025		lptimer2: timer@50021000 {
1026			#address-cells = <1>;
1027			#size-cells = <0>;
1028			compatible = "st,stm32-lptimer";
1029			reg = <0x50021000 0x400>;
1030			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1031			clocks = <&rcc LPTIM2_K>;
1032			clock-names = "mux";
1033			wakeup-source;
1034			status = "disabled";
1035
1036			pwm {
1037				compatible = "st,stm32-pwm-lp";
1038				#pwm-cells = <3>;
1039				status = "disabled";
1040			};
1041
1042			trigger@1 {
1043				compatible = "st,stm32-lptimer-trigger";
1044				reg = <1>;
1045				status = "disabled";
1046			};
1047
1048			counter {
1049				compatible = "st,stm32-lptimer-counter";
1050				status = "disabled";
1051			};
1052
1053			timer {
1054				compatible = "st,stm32-lptimer-timer";
1055				status = "disabled";
1056			};
1057		};
1058
1059		lptimer3: timer@50022000 {
1060			#address-cells = <1>;
1061			#size-cells = <0>;
1062			compatible = "st,stm32-lptimer";
1063			reg = <0x50022000 0x400>;
1064			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1065			clocks = <&rcc LPTIM3_K>;
1066			clock-names = "mux";
1067			wakeup-source;
1068			status = "disabled";
1069
1070			pwm {
1071				compatible = "st,stm32-pwm-lp";
1072				#pwm-cells = <3>;
1073				status = "disabled";
1074			};
1075
1076			trigger@2 {
1077				compatible = "st,stm32-lptimer-trigger";
1078				reg = <2>;
1079				status = "disabled";
1080			};
1081
1082			timer {
1083				compatible = "st,stm32-lptimer-timer";
1084				status = "disabled";
1085			};
1086		};
1087
1088		lptimer4: timer@50023000 {
1089			compatible = "st,stm32-lptimer";
1090			reg = <0x50023000 0x400>;
1091			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1092			clocks = <&rcc LPTIM4_K>;
1093			clock-names = "mux";
1094			wakeup-source;
1095			status = "disabled";
1096
1097			pwm {
1098				compatible = "st,stm32-pwm-lp";
1099				#pwm-cells = <3>;
1100				status = "disabled";
1101			};
1102
1103			timer {
1104				compatible = "st,stm32-lptimer-timer";
1105				status = "disabled";
1106			};
1107		};
1108
1109		lptimer5: timer@50024000 {
1110			compatible = "st,stm32-lptimer";
1111			reg = <0x50024000 0x400>;
1112			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1113			clocks = <&rcc LPTIM5_K>;
1114			clock-names = "mux";
1115			wakeup-source;
1116			status = "disabled";
1117
1118			pwm {
1119				compatible = "st,stm32-pwm-lp";
1120				#pwm-cells = <3>;
1121				status = "disabled";
1122			};
1123
1124			timer {
1125				compatible = "st,stm32-lptimer-timer";
1126				status = "disabled";
1127			};
1128		};
1129
1130		mdma: dma-controller@58000000 {
1131			compatible = "st,stm32h7-mdma";
1132			reg = <0x58000000 0x1000>;
1133			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1134			clocks = <&rcc MDMA>;
1135			#dma-cells = <5>;
1136			dma-channels = <32>;
1137			dma-requests = <48>;
1138		};
1139
1140		sdmmc1: mmc@58005000 {
1141			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1142			arm,primecell-periphid = <0x20253180>;
1143			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1144			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1145			clocks = <&rcc SDMMC1_K>;
1146			clock-names = "apb_pclk";
1147			resets = <&rcc SDMMC1_R>;
1148			cap-sd-highspeed;
1149			cap-mmc-highspeed;
1150			max-frequency = <130000000>;
1151			status = "disabled";
1152		};
1153
1154		sdmmc2: mmc@58007000 {
1155			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1156			arm,primecell-periphid = <0x20253180>;
1157			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1158			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1159			clocks = <&rcc SDMMC2_K>;
1160			clock-names = "apb_pclk";
1161			resets = <&rcc SDMMC2_R>;
1162			cap-sd-highspeed;
1163			cap-mmc-highspeed;
1164			max-frequency = <130000000>;
1165			status = "disabled";
1166		};
1167
1168		usbh_ohci: usb@5800c000 {
1169			compatible = "generic-ohci";
1170			reg = <0x5800c000 0x1000>;
1171			clocks = <&usbphyc>, <&rcc USBH>;
1172			resets = <&rcc USBH_R>;
1173			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1174			status = "disabled";
1175		};
1176
1177		usbh_ehci: usb@5800d000 {
1178			compatible = "generic-ehci";
1179			reg = <0x5800d000 0x1000>;
1180			clocks = <&usbphyc>, <&rcc USBH>;
1181			resets = <&rcc USBH_R>;
1182			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1183			companion = <&usbh_ohci>;
1184			status = "disabled";
1185		};
1186
1187		iwdg2: watchdog@5a002000 {
1188			compatible = "st,stm32mp1-iwdg";
1189			reg = <0x5a002000 0x400>;
1190			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1191			clock-names = "pclk", "lsi";
1192			status = "disabled";
1193		};
1194
1195		usbphyc: usbphyc@5a006000 {
1196			#address-cells = <1>;
1197			#size-cells = <0>;
1198			#clock-cells = <0>;
1199			compatible = "st,stm32mp1-usbphyc";
1200			reg = <0x5a006000 0x1000>;
1201			clocks = <&rcc USBPHY_K>;
1202			resets = <&rcc USBPHY_R>;
1203			vdda1v1-supply = <&reg11>;
1204			vdda1v8-supply = <&reg18>;
1205			status = "disabled";
1206
1207			usbphyc_port0: usb-phy@0 {
1208				#phy-cells = <0>;
1209				reg = <0>;
1210			};
1211
1212			usbphyc_port1: usb-phy@1 {
1213				#phy-cells = <1>;
1214				reg = <1>;
1215			};
1216		};
1217
1218		rtc: rtc@5c004000 {
1219			compatible = "st,stm32mp1-rtc";
1220			reg = <0x5c004000 0x400>;
1221			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1222			clocks = <&scmi_clk CK_SCMI_RTCAPB>,
1223				 <&scmi_clk CK_SCMI_RTC>;
1224			clock-names = "pclk", "rtc_ck";
1225			status = "disabled";
1226		};
1227
1228		bsec: efuse@5c005000 {
1229			compatible = "st,stm32mp13-bsec";
1230			reg = <0x5c005000 0x400>;
1231			#address-cells = <1>;
1232			#size-cells = <1>;
1233
1234			part_number_otp: part_number_otp@4 {
1235				reg = <0x4 0x2>;
1236				bits = <0 12>;
1237			};
1238			ts_cal1: calib@5c {
1239				reg = <0x5c 0x2>;
1240			};
1241			ts_cal2: calib@5e {
1242				reg = <0x5e 0x2>;
1243			};
1244		};
1245
1246		/*
1247		 * Break node order to solve dependency probe issue between
1248		 * pinctrl and exti.
1249		 */
1250		pinctrl: pinctrl@50002000 {
1251			#address-cells = <1>;
1252			#size-cells = <1>;
1253			compatible = "st,stm32mp135-pinctrl";
1254			ranges = <0 0x50002000 0x8400>;
1255			interrupt-parent = <&exti>;
1256			st,syscfg = <&exti 0x60 0xff>;
1257
1258			gpioa: gpio@50002000 {
1259				gpio-controller;
1260				#gpio-cells = <2>;
1261				interrupt-controller;
1262				#interrupt-cells = <2>;
1263				reg = <0x0 0x400>;
1264				clocks = <&rcc GPIOA>;
1265				st,bank-name = "GPIOA";
1266				ngpios = <16>;
1267				gpio-ranges = <&pinctrl 0 0 16>;
1268			};
1269
1270			gpiob: gpio@50003000 {
1271				gpio-controller;
1272				#gpio-cells = <2>;
1273				interrupt-controller;
1274				#interrupt-cells = <2>;
1275				reg = <0x1000 0x400>;
1276				clocks = <&rcc GPIOB>;
1277				st,bank-name = "GPIOB";
1278				ngpios = <16>;
1279				gpio-ranges = <&pinctrl 0 16 16>;
1280			};
1281
1282			gpioc: gpio@50004000 {
1283				gpio-controller;
1284				#gpio-cells = <2>;
1285				interrupt-controller;
1286				#interrupt-cells = <2>;
1287				reg = <0x2000 0x400>;
1288				clocks = <&rcc GPIOC>;
1289				st,bank-name = "GPIOC";
1290				ngpios = <16>;
1291				gpio-ranges = <&pinctrl 0 32 16>;
1292			};
1293
1294			gpiod: gpio@50005000 {
1295				gpio-controller;
1296				#gpio-cells = <2>;
1297				interrupt-controller;
1298				#interrupt-cells = <2>;
1299				reg = <0x3000 0x400>;
1300				clocks = <&rcc GPIOD>;
1301				st,bank-name = "GPIOD";
1302				ngpios = <16>;
1303				gpio-ranges = <&pinctrl 0 48 16>;
1304			};
1305
1306			gpioe: gpio@50006000 {
1307				gpio-controller;
1308				#gpio-cells = <2>;
1309				interrupt-controller;
1310				#interrupt-cells = <2>;
1311				reg = <0x4000 0x400>;
1312				clocks = <&rcc GPIOE>;
1313				st,bank-name = "GPIOE";
1314				ngpios = <16>;
1315				gpio-ranges = <&pinctrl 0 64 16>;
1316			};
1317
1318			gpiof: gpio@50007000 {
1319				gpio-controller;
1320				#gpio-cells = <2>;
1321				interrupt-controller;
1322				#interrupt-cells = <2>;
1323				reg = <0x5000 0x400>;
1324				clocks = <&rcc GPIOF>;
1325				st,bank-name = "GPIOF";
1326				ngpios = <16>;
1327				gpio-ranges = <&pinctrl 0 80 16>;
1328			};
1329
1330			gpiog: gpio@50008000 {
1331				gpio-controller;
1332				#gpio-cells = <2>;
1333				interrupt-controller;
1334				#interrupt-cells = <2>;
1335				reg = <0x6000 0x400>;
1336				clocks = <&rcc GPIOG>;
1337				st,bank-name = "GPIOG";
1338				ngpios = <16>;
1339				gpio-ranges = <&pinctrl 0 96 16>;
1340			};
1341
1342			gpioh: gpio@50009000 {
1343				gpio-controller;
1344				#gpio-cells = <2>;
1345				interrupt-controller;
1346				#interrupt-cells = <2>;
1347				reg = <0x7000 0x400>;
1348				clocks = <&rcc GPIOH>;
1349				st,bank-name = "GPIOH";
1350				ngpios = <15>;
1351				gpio-ranges = <&pinctrl 0 112 15>;
1352			};
1353
1354			gpioi: gpio@5000a000 {
1355				gpio-controller;
1356				#gpio-cells = <2>;
1357				interrupt-controller;
1358				#interrupt-cells = <2>;
1359				reg = <0x8000 0x400>;
1360				clocks = <&rcc GPIOI>;
1361				st,bank-name = "GPIOI";
1362				ngpios = <8>;
1363				gpio-ranges = <&pinctrl 0 128 8>;
1364			};
1365		};
1366	};
1367};
1368