1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/input/gpio-keys.h> 4#include <dt-bindings/input/input.h> 5#include <dt-bindings/power/summit,smb347-charger.h> 6#include <dt-bindings/thermal/thermal.h> 7 8#include "tegra30.dtsi" 9#include "tegra30-cpu-opp.dtsi" 10#include "tegra30-cpu-opp-microvolt.dtsi" 11#include "tegra30-asus-lvds-display.dtsi" 12 13/ { 14 aliases { 15 mmc0 = &sdmmc4; /* eMMC */ 16 mmc1 = &sdmmc3; /* WiFi */ 17 18 rtc0 = &pmic; 19 rtc1 = "/rtc@7000e000"; 20 21 serial1 = &uartc; /* Bluetooth */ 22 serial2 = &uartb; /* GPS */ 23 }; 24 25 /* 26 * The decompressor and also some bootloaders rely on a 27 * pre-existing /chosen node to be available to insert the 28 * command line and merge other ATAGS info. 29 */ 30 chosen {}; 31 32 firmware { 33 trusted-foundations { 34 compatible = "tlm,trusted-foundations"; 35 tlm,version-major = <0x0>; 36 tlm,version-minor = <0x0>; 37 }; 38 }; 39 40 memory@80000000 { 41 reg = <0x80000000 0x40000000>; 42 }; 43 44 reserved-memory { 45 #address-cells = <1>; 46 #size-cells = <1>; 47 ranges; 48 49 linux,cma@80000000 { 50 compatible = "shared-dma-pool"; 51 alloc-ranges = <0x80000000 0x30000000>; 52 size = <0x10000000>; /* 256MiB */ 53 linux,cma-default; 54 reusable; 55 }; 56 57 ramoops@bfdf0000 { 58 compatible = "ramoops"; 59 reg = <0xbfdf0000 0x10000>; /* 64kB */ 60 console-size = <0x8000>; /* 32kB */ 61 record-size = <0x400>; /* 1kB */ 62 ecc-size = <16>; 63 }; 64 65 trustzone@bfe00000 { 66 reg = <0xbfe00000 0x200000>; 67 no-map; 68 }; 69 }; 70 71 gpio@6000d000 { 72 init-low-power-mode-hog { 73 gpio-hog; 74 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 75 input; 76 }; 77 78 init-mode-hog { 79 gpio-hog; 80 gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, 81 <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, 82 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 83 output-low; 84 }; 85 }; 86 87 pinmux@70000868 { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&state_default>; 90 91 state_default: pinmux { 92 clk_32k_out_pa0 { 93 nvidia,pins = "clk_32k_out_pa0"; 94 nvidia,function = "blink"; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 96 nvidia,tristate = <TEGRA_PIN_DISABLE>; 97 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 98 }; 99 uart3_cts_n_pa1 { 100 nvidia,pins = "uart3_cts_n_pa1", 101 "uart3_rxd_pw7"; 102 nvidia,function = "uartc"; 103 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 104 nvidia,tristate = <TEGRA_PIN_DISABLE>; 105 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 106 }; 107 dap2_fs_pa2 { 108 nvidia,pins = "dap2_fs_pa2", 109 "dap2_sclk_pa3", 110 "dap2_din_pa4", 111 "dap2_dout_pa5"; 112 nvidia,function = "i2s1"; 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 114 nvidia,tristate = <TEGRA_PIN_DISABLE>; 115 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 116 }; 117 sdmmc3_clk_pa6 { 118 nvidia,pins = "sdmmc3_clk_pa6"; 119 nvidia,function = "sdmmc3"; 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 121 nvidia,tristate = <TEGRA_PIN_DISABLE>; 122 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 123 }; 124 sdmmc3_cmd_pa7 { 125 nvidia,pins = "sdmmc3_cmd_pa7", 126 "sdmmc3_dat3_pb4", 127 "sdmmc3_dat2_pb5", 128 "sdmmc3_dat1_pb6", 129 "sdmmc3_dat0_pb7", 130 "sdmmc3_dat4_pd1", 131 "sdmmc3_dat6_pd3", 132 "sdmmc3_dat7_pd4"; 133 nvidia,function = "sdmmc3"; 134 nvidia,pull = <TEGRA_PIN_PULL_UP>; 135 nvidia,tristate = <TEGRA_PIN_DISABLE>; 136 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 137 }; 138 gmi_a17_pb0 { 139 nvidia,pins = "gmi_a17_pb0", 140 "gmi_a18_pb1"; 141 nvidia,function = "uartd"; 142 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 143 nvidia,tristate = <TEGRA_PIN_DISABLE>; 144 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 145 }; 146 lcd_pwr0_pb2 { 147 nvidia,pins = "lcd_pwr0_pb2", 148 "lcd_pwr1_pc1", 149 "lcd_m1_pw1"; 150 nvidia,function = "displaya"; 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 152 nvidia,tristate = <TEGRA_PIN_DISABLE>; 153 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 154 }; 155 lcd_pclk_pb3 { 156 nvidia,pins = "lcd_pclk_pb3", 157 "lcd_d0_pe0", 158 "lcd_d1_pe1", 159 "lcd_d2_pe2", 160 "lcd_d3_pe3", 161 "lcd_d4_pe4", 162 "lcd_d5_pe5", 163 "lcd_d6_pe6", 164 "lcd_d7_pe7", 165 "lcd_d8_pf0", 166 "lcd_d9_pf1", 167 "lcd_d10_pf2", 168 "lcd_d11_pf3", 169 "lcd_d12_pf4", 170 "lcd_d13_pf5", 171 "lcd_d14_pf6", 172 "lcd_d15_pf7", 173 "lcd_de_pj1", 174 "lcd_hsync_pj3", 175 "lcd_vsync_pj4", 176 "lcd_d16_pm0", 177 "lcd_d17_pm1", 178 "lcd_d18_pm2", 179 "lcd_d19_pm3", 180 "lcd_d20_pm4", 181 "lcd_d21_pm5", 182 "lcd_d22_pm6", 183 "lcd_d23_pm7", 184 "lcd_cs0_n_pn4", 185 "lcd_sdout_pn5", 186 "lcd_dc0_pn6", 187 "lcd_cs1_n_pw0", 188 "lcd_sdin_pz2", 189 "lcd_sck_pz4"; 190 nvidia,function = "displaya"; 191 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 192 nvidia,tristate = <TEGRA_PIN_DISABLE>; 193 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 194 }; 195 uart3_rts_n_pc0 { 196 nvidia,pins = "uart3_rts_n_pc0", 197 "uart3_txd_pw6"; 198 nvidia,function = "uartc"; 199 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 200 nvidia,tristate = <TEGRA_PIN_DISABLE>; 201 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 202 }; 203 uart2_txd_pc2 { 204 nvidia,pins = "uart2_txd_pc2", 205 "uart2_rts_n_pj6"; 206 nvidia,function = "uartb"; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>; 209 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 210 }; 211 uart2_rxd_pc3 { 212 nvidia,pins = "uart2_rxd_pc3", 213 "uart2_cts_n_pj5"; 214 nvidia,function = "uartb"; 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>; 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218 }; 219 gen1_i2c_scl_pc4 { 220 nvidia,pins = "gen1_i2c_scl_pc4", 221 "gen1_i2c_sda_pc5"; 222 nvidia,function = "i2c1"; 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 224 nvidia,tristate = <TEGRA_PIN_DISABLE>; 225 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 226 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 227 }; 228 gmi_wp_n_pc7 { 229 nvidia,pins = "gmi_wp_n_pc7", 230 "gmi_wait_pi7", 231 "gmi_cs4_n_pk2", 232 "gmi_cs3_n_pk4"; 233 nvidia,function = "rsvd1"; 234 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 235 nvidia,tristate = <TEGRA_PIN_ENABLE>; 236 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 237 }; 238 gmi_ad12_ph4 { 239 nvidia,pins = "gmi_ad12_ph4", 240 "gmi_cs0_n_pj0", 241 "gmi_cs1_n_pj2", 242 "gmi_cs2_n_pk3"; 243 nvidia,function = "rsvd1"; 244 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 245 nvidia,tristate = <TEGRA_PIN_ENABLE>; 246 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 247 }; 248 sdmmc3_dat5_pd0 { 249 nvidia,pins = "sdmmc3_dat5_pd0"; 250 nvidia,function = "sdmmc3"; 251 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 252 nvidia,tristate = <TEGRA_PIN_DISABLE>; 253 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 254 }; 255 gmi_ad0_pg0 { 256 nvidia,pins = "gmi_ad0_pg0", 257 "gmi_ad1_pg1", 258 "gmi_ad14_ph6", 259 "pu1"; 260 nvidia,function = "rsvd1"; 261 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 262 nvidia,tristate = <TEGRA_PIN_DISABLE>; 263 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 264 }; 265 gmi_ad2_pg2 { 266 nvidia,pins = "gmi_ad2_pg2", 267 "gmi_ad3_pg3", 268 "gmi_ad6_pg6", 269 "gmi_ad7_pg7"; 270 nvidia,function = "rsvd1"; 271 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 272 nvidia,tristate = <TEGRA_PIN_DISABLE>; 273 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 274 }; 275 gmi_ad4_pg4 { 276 nvidia,pins = "gmi_ad4_pg4", 277 "gmi_ad5_pg5"; 278 nvidia,function = "nand"; 279 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 280 nvidia,tristate = <TEGRA_PIN_DISABLE>; 281 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 282 }; 283 gmi_ad8_ph0 { 284 nvidia,pins = "gmi_ad8_ph0"; 285 nvidia,function = "pwm0"; 286 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 287 nvidia,tristate = <TEGRA_PIN_DISABLE>; 288 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 289 }; 290 gmi_ad9_ph1 { 291 nvidia,pins = "gmi_ad9_ph1"; 292 nvidia,function = "rsvd4"; 293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 294 nvidia,tristate = <TEGRA_PIN_DISABLE>; 295 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 296 }; 297 gmi_ad10_ph2 { 298 nvidia,pins = "gmi_ad10_ph2"; 299 nvidia,function = "pwm2"; 300 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 301 nvidia,tristate = <TEGRA_PIN_ENABLE>; 302 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 303 }; 304 gmi_ad11_ph3 { 305 nvidia,pins = "gmi_ad11_ph3"; 306 nvidia,function = "pwm3"; 307 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 308 nvidia,tristate = <TEGRA_PIN_DISABLE>; 309 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 310 }; 311 gmi_ad13_ph5 { 312 nvidia,pins = "gmi_ad13_ph5", 313 "gmi_wr_n_pi0", 314 "gmi_oe_n_pi1", 315 "gmi_adv_n_pk0"; 316 nvidia,function = "rsvd1"; 317 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 318 nvidia,tristate = <TEGRA_PIN_ENABLE>; 319 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 320 }; 321 gmi_ad15_ph7 { 322 nvidia,pins = "gmi_ad15_ph7"; 323 nvidia,function = "rsvd1"; 324 nvidia,pull = <TEGRA_PIN_PULL_UP>; 325 nvidia,tristate = <TEGRA_PIN_DISABLE>; 326 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 327 }; 328 gmi_dqs_pi2 { 329 nvidia,pins = "gmi_dqs_pi2", 330 "pu2", 331 "pv1"; 332 nvidia,function = "rsvd1"; 333 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 334 nvidia,tristate = <TEGRA_PIN_DISABLE>; 335 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 336 }; 337 gmi_rst_n_pi4 { 338 nvidia,pins = "gmi_rst_n_pi4"; 339 nvidia,function = "nand"; 340 nvidia,pull = <TEGRA_PIN_PULL_UP>; 341 nvidia,tristate = <TEGRA_PIN_DISABLE>; 342 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 343 }; 344 gmi_iordy_pi5 { 345 nvidia,pins = "gmi_iordy_pi5"; 346 nvidia,function = "rsvd1"; 347 nvidia,pull = <TEGRA_PIN_PULL_UP>; 348 nvidia,tristate = <TEGRA_PIN_DISABLE>; 349 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 350 }; 351 gmi_cs7_n_pi6 { 352 nvidia,pins = "gmi_cs7_n_pi6", 353 "gmi_clk_pk1"; 354 nvidia,function = "nand"; 355 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 356 nvidia,tristate = <TEGRA_PIN_ENABLE>; 357 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 358 }; 359 gmi_a16_pj7 { 360 nvidia,pins = "gmi_a16_pj7", 361 "gmi_a19_pk7"; 362 nvidia,function = "uartd"; 363 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 364 nvidia,tristate = <TEGRA_PIN_DISABLE>; 365 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 366 }; 367 spdif_out_pk5 { 368 nvidia,pins = "spdif_out_pk5"; 369 nvidia,function = "spdif"; 370 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 371 nvidia,tristate = <TEGRA_PIN_DISABLE>; 372 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 373 }; 374 spdif_in_pk6 { 375 nvidia,pins = "spdif_in_pk6"; 376 nvidia,function = "spdif"; 377 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 378 nvidia,tristate = <TEGRA_PIN_DISABLE>; 379 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 380 }; 381 dap1_fs_pn0 { 382 nvidia,pins = "dap1_fs_pn0", 383 "dap1_din_pn1", 384 "dap1_dout_pn2", 385 "dap1_sclk_pn3"; 386 nvidia,function = "i2s0"; 387 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 388 nvidia,tristate = <TEGRA_PIN_DISABLE>; 389 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 390 }; 391 hdmi_int_pn7 { 392 nvidia,pins = "hdmi_int_pn7"; 393 nvidia,function = "hdmi"; 394 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 395 nvidia,tristate = <TEGRA_PIN_ENABLE>; 396 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 397 }; 398 ulpi_data7_po0 { 399 nvidia,pins = "ulpi_data7_po0"; 400 nvidia,function = "uarta"; 401 nvidia,pull = <TEGRA_PIN_PULL_UP>; 402 nvidia,tristate = <TEGRA_PIN_ENABLE>; 403 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 404 }; 405 ulpi_data3_po4 { 406 nvidia,pins = "ulpi_data3_po4"; 407 nvidia,function = "ulpi"; 408 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 409 nvidia,tristate = <TEGRA_PIN_DISABLE>; 410 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 411 }; 412 dap3_fs_pp0 { 413 nvidia,pins = "dap3_fs_pp0"; 414 nvidia,function = "i2s2"; 415 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 416 nvidia,tristate = <TEGRA_PIN_DISABLE>; 417 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 418 }; 419 dap4_fs_pp4 { 420 nvidia,pins = "dap4_fs_pp4", 421 "dap4_din_pp5", 422 "dap4_dout_pp6", 423 "dap4_sclk_pp7"; 424 nvidia,function = "i2s3"; 425 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 426 nvidia,tristate = <TEGRA_PIN_DISABLE>; 427 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 428 }; 429 kb_col0_pq0 { 430 nvidia,pins = "kb_col0_pq0", 431 "kb_col1_pq1", 432 "kb_row1_pr1"; 433 nvidia,function = "kbc"; 434 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435 nvidia,tristate = <TEGRA_PIN_ENABLE>; 436 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 437 }; 438 kb_col2_pq2 { 439 nvidia,pins = "kb_col2_pq2", 440 "kb_col3_pq3"; 441 nvidia,function = "rsvd4"; 442 nvidia,pull = <TEGRA_PIN_PULL_UP>; 443 nvidia,tristate = <TEGRA_PIN_ENABLE>; 444 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 445 }; 446 kb_col4_pq4 { 447 nvidia,pins = "kb_col4_pq4", 448 "kb_col5_pq5", 449 "kb_col7_pq7", 450 "kb_row2_pr2", 451 "kb_row4_pr4", 452 "kb_row5_pr5", 453 "kb_row14_ps6"; 454 nvidia,function = "kbc"; 455 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 456 nvidia,tristate = <TEGRA_PIN_ENABLE>; 457 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 458 }; 459 kb_row0_pr0 { 460 nvidia,pins = "kb_row0_pr0"; 461 nvidia,function = "rsvd4"; 462 nvidia,pull = <TEGRA_PIN_PULL_UP>; 463 nvidia,tristate = <TEGRA_PIN_DISABLE>; 464 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 465 }; 466 kb_row6_pr6 { 467 nvidia,pins = "kb_row6_pr6", 468 "kb_row8_ps0", 469 "kb_row9_ps1", 470 "kb_row10_ps2"; 471 nvidia,function = "kbc"; 472 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 473 nvidia,tristate = <TEGRA_PIN_DISABLE>; 474 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 475 }; 476 kb_row11_ps3 { 477 nvidia,pins = "kb_row11_ps3", 478 "kb_row12_ps4"; 479 nvidia,function = "kbc"; 480 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 481 nvidia,tristate = <TEGRA_PIN_DISABLE>; 482 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 483 }; 484 gen2_i2c_scl_pt5 { 485 nvidia,pins = "gen2_i2c_scl_pt5", 486 "gen2_i2c_sda_pt6"; 487 nvidia,function = "i2c2"; 488 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 489 nvidia,tristate = <TEGRA_PIN_DISABLE>; 490 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 491 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 492 }; 493 sdmmc4_cmd_pt7 { 494 nvidia,pins = "sdmmc4_cmd_pt7", 495 "sdmmc4_dat0_paa0", 496 "sdmmc4_dat1_paa1", 497 "sdmmc4_dat2_paa2", 498 "sdmmc4_dat3_paa3", 499 "sdmmc4_dat4_paa4", 500 "sdmmc4_dat5_paa5", 501 "sdmmc4_dat6_paa6", 502 "sdmmc4_dat7_paa7"; 503 nvidia,function = "sdmmc4"; 504 nvidia,pull = <TEGRA_PIN_PULL_UP>; 505 nvidia,tristate = <TEGRA_PIN_DISABLE>; 506 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 507 }; 508 pu0 { 509 nvidia,pins = "pu0", 510 "pu6"; 511 nvidia,function = "rsvd4"; 512 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 513 nvidia,tristate = <TEGRA_PIN_DISABLE>; 514 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515 }; 516 jtag_rtck_pu7 { 517 nvidia,pins = "jtag_rtck_pu7"; 518 nvidia,function = "rtck"; 519 nvidia,pull = <TEGRA_PIN_PULL_UP>; 520 nvidia,tristate = <TEGRA_PIN_DISABLE>; 521 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 522 }; 523 pv0 { 524 nvidia,pins = "pv0"; 525 nvidia,function = "rsvd1"; 526 nvidia,pull = <TEGRA_PIN_PULL_UP>; 527 nvidia,tristate = <TEGRA_PIN_ENABLE>; 528 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 529 }; 530 ddc_scl_pv4 { 531 nvidia,pins = "ddc_scl_pv4", 532 "ddc_sda_pv5"; 533 nvidia,function = "i2c4"; 534 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 535 nvidia,tristate = <TEGRA_PIN_DISABLE>; 536 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 537 }; 538 crt_hsync_pv6 { 539 nvidia,pins = "crt_hsync_pv6", 540 "crt_vsync_pv7"; 541 nvidia,function = "crt"; 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543 nvidia,tristate = <TEGRA_PIN_DISABLE>; 544 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 545 }; 546 spi2_cs1_n_pw2 { 547 nvidia,pins = "spi2_cs1_n_pw2", 548 "spi2_miso_px1", 549 "spi2_sck_px2"; 550 nvidia,function = "spi2"; 551 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 552 nvidia,tristate = <TEGRA_PIN_DISABLE>; 553 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 554 }; 555 clk1_out_pw4 { 556 nvidia,pins = "clk1_out_pw4"; 557 nvidia,function = "extperiph1"; 558 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 559 nvidia,tristate = <TEGRA_PIN_DISABLE>; 560 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 561 }; 562 clk2_out_pw5 { 563 nvidia,pins = "clk2_out_pw5"; 564 nvidia,function = "extperiph2"; 565 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 566 nvidia,tristate = <TEGRA_PIN_DISABLE>; 567 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 568 }; 569 spi2_cs0_n_px3 { 570 nvidia,pins = "spi2_cs0_n_px3"; 571 nvidia,function = "spi6"; 572 nvidia,pull = <TEGRA_PIN_PULL_UP>; 573 nvidia,tristate = <TEGRA_PIN_DISABLE>; 574 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 575 }; 576 spi1_mosi_px4 { 577 nvidia,pins = "spi1_mosi_px4", 578 "spi1_cs0_n_px6"; 579 nvidia,function = "spi1"; 580 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 581 nvidia,tristate = <TEGRA_PIN_DISABLE>; 582 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 583 }; 584 ulpi_clk_py0 { 585 nvidia,pins = "ulpi_clk_py0", 586 "ulpi_dir_py1"; 587 nvidia,function = "ulpi"; 588 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 589 nvidia,tristate = <TEGRA_PIN_ENABLE>; 590 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 591 }; 592 sdmmc1_dat3_py4 { 593 nvidia,pins = "sdmmc1_dat3_py4", 594 "sdmmc1_dat2_py5", 595 "sdmmc1_dat1_py6", 596 "sdmmc1_dat0_py7", 597 "sdmmc1_cmd_pz1"; 598 nvidia,function = "sdmmc1"; 599 nvidia,pull = <TEGRA_PIN_PULL_UP>; 600 nvidia,tristate = <TEGRA_PIN_DISABLE>; 601 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 602 }; 603 sdmmc1_clk_pz0 { 604 nvidia,pins = "sdmmc1_clk_pz0"; 605 nvidia,function = "sdmmc1"; 606 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 607 nvidia,tristate = <TEGRA_PIN_DISABLE>; 608 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 609 }; 610 lcd_wr_n_pz3 { 611 nvidia,pins = "lcd_wr_n_pz3"; 612 nvidia,function = "displaya"; 613 nvidia,pull = <TEGRA_PIN_PULL_UP>; 614 nvidia,tristate = <TEGRA_PIN_DISABLE>; 615 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 616 }; 617 sys_clk_req_pz5 { 618 nvidia,pins = "sys_clk_req_pz5"; 619 nvidia,function = "sysclk"; 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 621 nvidia,tristate = <TEGRA_PIN_DISABLE>; 622 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 623 }; 624 pwr_i2c_scl_pz6 { 625 nvidia,pins = "pwr_i2c_scl_pz6", 626 "pwr_i2c_sda_pz7"; 627 nvidia,function = "i2cpwr"; 628 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 629 nvidia,tristate = <TEGRA_PIN_DISABLE>; 630 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 631 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 632 }; 633 pbb0 { 634 nvidia,pins = "pbb0", 635 "pcc1"; 636 nvidia,function = "rsvd2"; 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638 nvidia,tristate = <TEGRA_PIN_DISABLE>; 639 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 640 }; 641 cam_i2c_scl_pbb1 { 642 nvidia,pins = "cam_i2c_scl_pbb1", 643 "cam_i2c_sda_pbb2"; 644 nvidia,function = "i2c3"; 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646 nvidia,tristate = <TEGRA_PIN_DISABLE>; 647 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 649 }; 650 pbb3 { 651 nvidia,pins = "pbb3"; 652 nvidia,function = "vgp3"; 653 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654 nvidia,tristate = <TEGRA_PIN_DISABLE>; 655 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 656 }; 657 pbb4 { 658 nvidia,pins = "pbb4"; 659 nvidia,function = "vgp4"; 660 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 661 nvidia,tristate = <TEGRA_PIN_DISABLE>; 662 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 663 }; 664 pbb5 { 665 nvidia,pins = "pbb5"; 666 nvidia,function = "vgp5"; 667 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 668 nvidia,tristate = <TEGRA_PIN_DISABLE>; 669 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 670 }; 671 pbb6 { 672 nvidia,pins = "pbb6"; 673 nvidia,function = "vgp6"; 674 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 675 nvidia,tristate = <TEGRA_PIN_DISABLE>; 676 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 677 }; 678 pbb7 { 679 nvidia,pins = "pbb7", 680 "pcc2"; 681 nvidia,function = "i2s4"; 682 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 683 nvidia,tristate = <TEGRA_PIN_DISABLE>; 684 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 685 }; 686 cam_mclk_pcc0 { 687 nvidia,pins = "cam_mclk_pcc0"; 688 nvidia,function = "vi_alt3"; 689 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 690 nvidia,tristate = <TEGRA_PIN_DISABLE>; 691 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 692 }; 693 sdmmc4_rst_n_pcc3 { 694 nvidia,pins = "sdmmc4_rst_n_pcc3"; 695 nvidia,function = "rsvd2"; 696 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 697 nvidia,tristate = <TEGRA_PIN_DISABLE>; 698 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 699 }; 700 sdmmc4_clk_pcc4 { 701 nvidia,pins = "sdmmc4_clk_pcc4"; 702 nvidia,function = "sdmmc4"; 703 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 704 nvidia,tristate = <TEGRA_PIN_DISABLE>; 705 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 706 }; 707 clk2_req_pcc5 { 708 nvidia,pins = "clk2_req_pcc5"; 709 nvidia,function = "dap"; 710 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711 nvidia,tristate = <TEGRA_PIN_DISABLE>; 712 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 713 }; 714 pex_l2_rst_n_pcc6 { 715 nvidia,pins = "pex_l2_rst_n_pcc6", 716 "pex_l2_clkreq_n_pcc7"; 717 nvidia,function = "pcie"; 718 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 719 nvidia,tristate = <TEGRA_PIN_DISABLE>; 720 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 721 }; 722 pex_wake_n_pdd3 { 723 nvidia,pins = "pex_wake_n_pdd3", 724 "pex_l2_prsnt_n_pdd7"; 725 nvidia,function = "pcie"; 726 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 727 nvidia,tristate = <TEGRA_PIN_DISABLE>; 728 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 729 }; 730 clk3_out_pee0 { 731 nvidia,pins = "clk3_out_pee0"; 732 nvidia,function = "extperiph3"; 733 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 734 nvidia,tristate = <TEGRA_PIN_DISABLE>; 735 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 736 }; 737 clk1_req_pee2 { 738 nvidia,pins = "clk1_req_pee2"; 739 nvidia,function = "dap"; 740 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 741 nvidia,tristate = <TEGRA_PIN_ENABLE>; 742 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 743 }; 744 hdmi_cec_pee3 { 745 nvidia,pins = "hdmi_cec_pee3"; 746 nvidia,function = "cec"; 747 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 748 nvidia,tristate = <TEGRA_PIN_DISABLE>; 749 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 750 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 751 }; 752 owr { 753 nvidia,pins = "owr"; 754 nvidia,function = "owr"; 755 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 756 nvidia,tristate = <TEGRA_PIN_DISABLE>; 757 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 758 }; 759 drive_dap1 { 760 nvidia,pins = "drive_dap1", 761 "drive_dap2", 762 "drive_dbg", 763 "drive_at5", 764 "drive_gme", 765 "drive_ddc", 766 "drive_ao1", 767 "drive_uart3"; 768 nvidia,high-speed-mode = <0>; 769 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 770 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 771 nvidia,pull-down-strength = <31>; 772 nvidia,pull-up-strength = <31>; 773 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 774 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 775 }; 776 drive_sdio1 { 777 nvidia,pins = "drive_sdio1", 778 "drive_sdio3"; 779 nvidia,high-speed-mode = <0>; 780 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 781 nvidia,pull-down-strength = <46>; 782 nvidia,pull-up-strength = <42>; 783 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 784 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 785 }; 786 drive_gma { 787 nvidia,pins = "drive_gma", 788 "drive_gmb", 789 "drive_gmc", 790 "drive_gmd"; 791 nvidia,pull-down-strength = <9>; 792 nvidia,pull-up-strength = <9>; 793 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 794 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 795 }; 796 }; 797 }; 798 799 uartb: serial@70006040 { 800 compatible = "nvidia,tegra30-hsuart"; 801 /delete-property/ reg-shift; 802 /* GPS BCM4751 */ 803 }; 804 805 uartc: serial@70006200 { 806 compatible = "nvidia,tegra30-hsuart"; 807 /delete-property/ reg-shift; 808 status = "okay"; 809 810 nvidia,adjust-baud-rates = <0 9600 100>, 811 <9600 115200 200>, 812 <1000000 4000000 136>; 813 814 /* Azurewave AW-NH665 BCM4330B1 */ 815 bluetooth { 816 compatible = "brcm,bcm4330-bt"; 817 818 interrupt-parent = <&gpio>; 819 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 820 interrupt-names = "host-wakeup"; 821 822 max-speed = <4000000>; 823 824 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 825 clock-names = "txco"; 826 827 vbat-supply = <&vdd_3v3_sys>; 828 vddio-supply = <&vdd_1v8>; 829 830 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 831 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 832 }; 833 }; 834 835 pwm: pwm@7000a000 { 836 status = "okay"; 837 }; 838 839 i2c@7000c400 { 840 clock-frequency = <400000>; 841 status = "okay"; 842 843 touchscreen@10 { 844 compatible = "elan,ektf3624"; 845 reg = <0x10>; 846 847 interrupt-parent = <&gpio>; 848 interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; 849 850 reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 851 852 vcc33-supply = <&vcc_3v3_ts>; 853 vccio-supply = <&vcc_3v3_ts>; 854 855 touchscreen-size-x = <2112>; 856 touchscreen-size-y = <1280>; 857 touchscreen-swapped-x-y; 858 touchscreen-inverted-x; 859 }; 860 }; 861 862 i2c@7000c500 { 863 clock-frequency = <100000>; 864 status = "okay"; 865 866 compass@e { 867 compatible = "asahi-kasei,ak8974"; 868 reg = <0x0e>; 869 870 interrupt-parent = <&gpio>; 871 interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; 872 873 avdd-supply = <&vdd_3v3_sys>; 874 dvdd-supply = <&vdd_1v8>; 875 876 mount-matrix = "0", "-1", "0", 877 "-1", "0", "0", 878 "0", "0", "-1"; 879 }; 880 881 light-sensor@1c { 882 compatible = "dynaimage,al3010"; 883 reg = <0x1c>; 884 885 interrupt-parent = <&gpio>; 886 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 887 888 vdd-supply = <&vdd_3v3_sys>; 889 }; 890 891 accelerometer@68 { 892 compatible = "invensense,mpu6050"; 893 reg = <0x68>; 894 895 interrupt-parent = <&gpio>; 896 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 897 898 vdd-supply = <&vdd_3v3_sys>; 899 vddio-supply = <&vdd_1v8>; 900 901 mount-matrix = "0", "-1", "0", 902 "-1", "0", "0", 903 "0", "0", "-1"; 904 }; 905 }; 906 907 i2c@7000d000 { 908 clock-frequency = <100000>; 909 status = "okay"; 910 911 rt5640: audio-codec@1c { 912 compatible = "realtek,rt5640"; 913 reg = <0x1c>; 914 915 realtek,dmic1-data-pin = <1>; 916 }; 917 918 nct72: temperature-sensor@4c { 919 compatible = "onnn,nct1008"; 920 reg = <0x4c>; 921 vcc-supply = <&vdd_3v3_sys>; 922 923 interrupt-parent = <&gpio>; 924 interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>; 925 926 #thermal-sensor-cells = <1>; 927 }; 928 929 fuel-gauge@55 { 930 compatible = "ti,bq27541"; 931 reg = <0x55>; 932 power-supplies = <&power_supply>; 933 }; 934 935 power_supply: charger@6a { 936 compatible = "summit,smb347"; 937 reg = <0x6a>; 938 939 interrupt-parent = <&gpio>; 940 interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; 941 942 summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; 943 summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; 944 summit,enable-usb-charging; 945 946 monitored-battery = <&battery_cell>; 947 948 usb_vbus: usb-vbus { 949 regulator-name = "usb_vbus"; 950 regulator-min-microvolt = <5000000>; 951 regulator-max-microvolt = <5000000>; 952 regulator-min-microamp = <750000>; 953 regulator-max-microamp = <750000>; 954 955 /* 956 * SMB347 INOK input pin is connected to PMIC's 957 * ACOK output, which is fixed to ACTIVE_LOW as 958 * long as battery voltage is in a good range. 959 * 960 * Active INOK disables SMB347 output, so polarity 961 * needs to be toggled when we want to get the 962 * output. 963 */ 964 summit,needs-inok-toggle; 965 }; 966 }; 967 }; 968 969 pmc@7000e400 { 970 status = "okay"; 971 nvidia,invert-interrupt; 972 nvidia,suspend-mode = <1>; 973 nvidia,cpu-pwr-good-time = <2000>; 974 nvidia,cpu-pwr-off-time = <200>; 975 nvidia,core-pwr-good-time = <3845 3845>; 976 nvidia,core-pwr-off-time = <0>; 977 nvidia,core-power-req-active-high; 978 nvidia,sys-clock-req-active-high; 979 core-supply = <&vdd_core>; 980 }; 981 982 ahub@70080000 { 983 i2s@70080400 { 984 status = "okay"; 985 }; 986 }; 987 988 sdmmc3: mmc@78000400 { 989 status = "okay"; 990 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 995 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 996 assigned-clock-rates = <50000000>; 997 998 max-frequency = <50000000>; 999 keep-power-in-suspend; 1000 bus-width = <4>; 1001 non-removable; 1002 1003 mmc-pwrseq = <&brcm_wifi_pwrseq>; 1004 vmmc-supply = <&vdd_3v3_sys>; 1005 vqmmc-supply = <&vdd_1v8>; 1006 1007 /* Azurewave AW-NH665 BCM4330 */ 1008 wifi@1 { 1009 reg = <1>; 1010 compatible = "brcm,bcm4329-fmac"; 1011 interrupt-parent = <&gpio>; 1012 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 1013 interrupt-names = "host-wake"; 1014 }; 1015 }; 1016 1017 sdmmc4: mmc@78000600 { 1018 status = "okay"; 1019 bus-width = <8>; 1020 vmmc-supply = <&vcore_emmc>; 1021 vqmmc-supply = <&vdd_1v8>; 1022 non-removable; 1023 }; 1024 1025 usb@7d000000 { 1026 compatible = "nvidia,tegra30-udc"; 1027 status = "okay"; 1028 dr_mode = "otg"; 1029 vbus-supply = <&usb_vbus>; 1030 }; 1031 1032 usb-phy@7d000000 { 1033 status = "okay"; 1034 dr_mode = "otg"; 1035 nvidia,hssync-start-delay = <0>; 1036 nvidia,xcvr-lsfslew = <2>; 1037 nvidia,xcvr-lsrslew = <2>; 1038 }; 1039 1040 backlight: backlight { 1041 compatible = "pwm-backlight"; 1042 1043 power-supply = <&vdd_5v0_sys>; 1044 pwms = <&pwm 0 50000>; 1045 1046 brightness-levels = <1 255>; 1047 num-interpolated-steps = <254>; 1048 default-brightness-level = <15>; 1049 }; 1050 1051 battery_cell: battery-cell { 1052 compatible = "simple-battery"; 1053 constant-charge-current-max-microamp = <1800000>; 1054 operating-range-celsius = <0 45>; 1055 }; 1056 1057 /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1058 clk32k_in: clock-32k { 1059 compatible = "fixed-clock"; 1060 #clock-cells = <0>; 1061 clock-frequency = <32768>; 1062 clock-output-names = "pmic-oscillator"; 1063 }; 1064 1065 cpus { 1066 cpu0: cpu@0 { 1067 cpu-supply = <&vdd_cpu>; 1068 operating-points-v2 = <&cpu0_opp_table>; 1069 #cooling-cells = <2>; 1070 }; 1071 1072 cpu1: cpu@1 { 1073 cpu-supply = <&vdd_cpu>; 1074 operating-points-v2 = <&cpu0_opp_table>; 1075 #cooling-cells = <2>; 1076 }; 1077 1078 cpu2: cpu@2 { 1079 cpu-supply = <&vdd_cpu>; 1080 operating-points-v2 = <&cpu0_opp_table>; 1081 #cooling-cells = <2>; 1082 }; 1083 1084 cpu3: cpu@3 { 1085 cpu-supply = <&vdd_cpu>; 1086 operating-points-v2 = <&cpu0_opp_table>; 1087 #cooling-cells = <2>; 1088 }; 1089 }; 1090 1091 display-panel { 1092 /* 1093 * Nexus 7 supports two compatible panel models: 1094 * 1095 * 1. hydis,hv070wx2-1e0 1096 * 2. chunghwa,claa070wp03xg 1097 * 1098 * We want to use timing which is optimized for Nexus 7, 1099 * hence we need to customize the timing. 1100 */ 1101 compatible = "panel-lvds"; 1102 1103 width-mm = <94>; 1104 height-mm = <150>; 1105 rotation = <180>; 1106 1107 data-mapping = "jeida-24"; 1108 1109 /* DDC unconnected on Nexus 7 */ 1110 /delete-property/ ddc-i2c-bus; 1111 }; 1112 1113 gpio-keys { 1114 compatible = "gpio-keys"; 1115 1116 key-power { 1117 label = "Power"; 1118 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1119 linux,code = <KEY_POWER>; 1120 debounce-interval = <10>; 1121 wakeup-event-action = <EV_ACT_ASSERTED>; 1122 wakeup-source; 1123 }; 1124 1125 key-volume-down { 1126 label = "Volume Down"; 1127 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; 1128 linux,code = <KEY_VOLUMEDOWN>; 1129 debounce-interval = <10>; 1130 wakeup-event-action = <EV_ACT_ASSERTED>; 1131 wakeup-source; 1132 }; 1133 1134 key-volume-up { 1135 label = "Volume Up"; 1136 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 1137 linux,code = <KEY_VOLUMEUP>; 1138 debounce-interval = <10>; 1139 wakeup-event-action = <EV_ACT_ASSERTED>; 1140 wakeup-source; 1141 }; 1142 1143 switch-hall-sensor { 1144 label = "Lid"; 1145 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; 1146 linux,input-type = <EV_SW>; 1147 linux,code = <SW_LID>; 1148 debounce-interval = <500>; 1149 wakeup-event-action = <EV_ACT_DEASSERTED>; 1150 wakeup-source; 1151 }; 1152 }; 1153 1154 brcm_wifi_pwrseq: pwrseq-wifi { 1155 compatible = "mmc-pwrseq-simple"; 1156 1157 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1158 clock-names = "ext_clock"; 1159 1160 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; 1161 post-power-on-delay-ms = <300>; 1162 power-off-delay-us = <300>; 1163 }; 1164 1165 vdd_5v0_sys: regulator-5v0 { 1166 compatible = "regulator-fixed"; 1167 regulator-name = "vdd_5v0"; 1168 regulator-min-microvolt = <5000000>; 1169 regulator-max-microvolt = <5000000>; 1170 regulator-always-on; 1171 regulator-boot-on; 1172 }; 1173 1174 vdd_3v3_sys: regulator-3v3 { 1175 compatible = "regulator-fixed"; 1176 regulator-name = "vdd_3v3"; 1177 regulator-min-microvolt = <3300000>; 1178 regulator-max-microvolt = <3300000>; 1179 regulator-always-on; 1180 regulator-boot-on; 1181 vin-supply = <&vdd_5v0_sys>; 1182 }; 1183 1184 vdd_pnl: regulator-panel { 1185 compatible = "regulator-fixed"; 1186 regulator-name = "vdd_panel"; 1187 regulator-min-microvolt = <3300000>; 1188 regulator-max-microvolt = <3300000>; 1189 regulator-enable-ramp-delay = <300000>; 1190 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1191 enable-active-high; 1192 vin-supply = <&vdd_3v3_sys>; 1193 }; 1194 1195 vcc_3v3_ts: regulator-ts { 1196 compatible = "regulator-fixed"; 1197 regulator-name = "ldo_s-1167_3v3"; 1198 regulator-min-microvolt = <3300000>; 1199 regulator-max-microvolt = <3300000>; 1200 regulator-always-on; 1201 regulator-boot-on; 1202 vin-supply = <&vdd_5v0_sys>; 1203 }; 1204 1205 sound { 1206 compatible = "nvidia,tegra-audio-rt5640-grouper", 1207 "nvidia,tegra-audio-rt5640"; 1208 nvidia,model = "ASUS Google Nexus 7 ALC5642"; 1209 1210 nvidia,audio-routing = 1211 "Headphones", "HPOR", 1212 "Headphones", "HPOL", 1213 "Speakers", "SPORP", 1214 "Speakers", "SPORN", 1215 "Speakers", "SPOLP", 1216 "Speakers", "SPOLN", 1217 "DMIC1", "Mic Jack"; 1218 1219 nvidia,i2s-controller = <&tegra_i2s1>; 1220 nvidia,audio-codec = <&rt5640>; 1221 1222 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1223 1224 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1225 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1226 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1227 clock-names = "pll_a", "pll_a_out0", "mclk"; 1228 1229 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1230 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1231 1232 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1233 <&tegra_car TEGRA30_CLK_EXTERN1>; 1234 }; 1235 1236 thermal-zones { 1237 /* 1238 * NCT72 has two sensors: 1239 * 1240 * 0: internal that monitors ambient/skin temperature 1241 * 1: external that is connected to the CPU's diode 1242 * 1243 * Ideally we should use userspace thermal governor, 1244 * but it's a much more complex solution. The "skin" 1245 * zone is a simpler solution which prevents Nexus 7 1246 * from getting too hot from a user's tactile perspective. 1247 * The CPU zone is intended to protect silicon from damage. 1248 */ 1249 1250 skin-thermal { 1251 polling-delay-passive = <1000>; /* milliseconds */ 1252 polling-delay = <5000>; /* milliseconds */ 1253 1254 thermal-sensors = <&nct72 0>; 1255 1256 trips { 1257 trip0: skin-alert { 1258 /* throttle at 57C until temperature drops to 56.8C */ 1259 temperature = <57000>; 1260 hysteresis = <200>; 1261 type = "passive"; 1262 }; 1263 1264 trip1: skin-crit { 1265 /* shut down at 65C */ 1266 temperature = <65000>; 1267 hysteresis = <2000>; 1268 type = "critical"; 1269 }; 1270 }; 1271 1272 cooling-maps { 1273 map0 { 1274 trip = <&trip0>; 1275 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1276 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1277 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1278 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1279 <&actmon THERMAL_NO_LIMIT 1280 THERMAL_NO_LIMIT>; 1281 }; 1282 }; 1283 }; 1284 1285 cpu-thermal { 1286 polling-delay-passive = <1000>; /* milliseconds */ 1287 polling-delay = <5000>; /* milliseconds */ 1288 1289 thermal-sensors = <&nct72 1>; 1290 1291 trips { 1292 trip2: cpu-alert { 1293 /* throttle at 85C until temperature drops to 84.8C */ 1294 temperature = <85000>; 1295 hysteresis = <200>; 1296 type = "passive"; 1297 }; 1298 1299 trip3: cpu-crit { 1300 /* shut down at 90C */ 1301 temperature = <90000>; 1302 hysteresis = <2000>; 1303 type = "critical"; 1304 }; 1305 }; 1306 1307 cooling-maps { 1308 map1 { 1309 trip = <&trip2>; 1310 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1311 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1312 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1313 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1314 <&actmon THERMAL_NO_LIMIT 1315 THERMAL_NO_LIMIT>; 1316 }; 1317 }; 1318 }; 1319 }; 1320}; 1321