1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "socionext,uniphier-ld4"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 reg = <0>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 }; 27 }; 28 29 psci { 30 compatible = "arm,psci-0.2"; 31 method = "smc"; 32 }; 33 34 clocks { 35 refclk: ref { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <24576000>; 39 }; 40 41 arm_timer_clk: arm-timer { 42 #clock-cells = <0>; 43 compatible = "fixed-clock"; 44 clock-frequency = <50000000>; 45 }; 46 }; 47 48 soc { 49 compatible = "simple-bus"; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges; 53 interrupt-parent = <&intc>; 54 55 l2: cache-controller@500c0000 { 56 compatible = "socionext,uniphier-system-cache"; 57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 58 <0x506c0000 0x400>; 59 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 61 cache-unified; 62 cache-size = <(512 * 1024)>; 63 cache-sets = <256>; 64 cache-line-size = <128>; 65 cache-level = <2>; 66 }; 67 68 spi: spi@54006000 { 69 compatible = "socionext,uniphier-scssi"; 70 status = "disabled"; 71 reg = <0x54006000 0x100>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_spi0>; 77 clocks = <&peri_clk 11>; 78 resets = <&peri_rst 11>; 79 }; 80 81 serial0: serial@54006800 { 82 compatible = "socionext,uniphier-uart"; 83 status = "disabled"; 84 reg = <0x54006800 0x40>; 85 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_uart0>; 88 clocks = <&peri_clk 0>; 89 resets = <&peri_rst 0>; 90 }; 91 92 serial1: serial@54006900 { 93 compatible = "socionext,uniphier-uart"; 94 status = "disabled"; 95 reg = <0x54006900 0x40>; 96 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_uart1>; 99 clocks = <&peri_clk 1>; 100 resets = <&peri_rst 1>; 101 }; 102 103 serial2: serial@54006a00 { 104 compatible = "socionext,uniphier-uart"; 105 status = "disabled"; 106 reg = <0x54006a00 0x40>; 107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_uart2>; 110 clocks = <&peri_clk 2>; 111 resets = <&peri_rst 2>; 112 }; 113 114 serial3: serial@54006b00 { 115 compatible = "socionext,uniphier-uart"; 116 status = "disabled"; 117 reg = <0x54006b00 0x40>; 118 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_uart3>; 121 clocks = <&peri_clk 3>; 122 resets = <&peri_rst 3>; 123 }; 124 125 gpio: gpio@55000000 { 126 compatible = "socionext,uniphier-gpio"; 127 reg = <0x55000000 0x200>; 128 interrupt-parent = <&aidet>; 129 interrupt-controller; 130 #interrupt-cells = <2>; 131 gpio-controller; 132 #gpio-cells = <2>; 133 gpio-ranges = <&pinctrl 0 0 0>; 134 gpio-ranges-group-names = "gpio_range"; 135 ngpios = <136>; 136 socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 137 }; 138 139 i2c0: i2c@58400000 { 140 compatible = "socionext,uniphier-i2c"; 141 status = "disabled"; 142 reg = <0x58400000 0x40>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_i2c0>; 148 clocks = <&peri_clk 4>; 149 resets = <&peri_rst 4>; 150 clock-frequency = <100000>; 151 }; 152 153 i2c1: i2c@58480000 { 154 compatible = "socionext,uniphier-i2c"; 155 status = "disabled"; 156 reg = <0x58480000 0x40>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_i2c1>; 162 clocks = <&peri_clk 5>; 163 resets = <&peri_rst 5>; 164 clock-frequency = <100000>; 165 }; 166 167 /* chip-internal connection for DMD */ 168 i2c2: i2c@58500000 { 169 compatible = "socionext,uniphier-i2c"; 170 reg = <0x58500000 0x40>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_i2c2>; 176 clocks = <&peri_clk 6>; 177 resets = <&peri_rst 6>; 178 clock-frequency = <400000>; 179 }; 180 181 i2c3: i2c@58580000 { 182 compatible = "socionext,uniphier-i2c"; 183 status = "disabled"; 184 reg = <0x58580000 0x40>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_i2c3>; 190 clocks = <&peri_clk 7>; 191 resets = <&peri_rst 7>; 192 clock-frequency = <100000>; 193 }; 194 195 system_bus: system-bus@58c00000 { 196 compatible = "socionext,uniphier-system-bus"; 197 status = "disabled"; 198 reg = <0x58c00000 0x400>; 199 #address-cells = <2>; 200 #size-cells = <1>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_system_bus>; 203 }; 204 205 smpctrl@59801000 { 206 compatible = "socionext,uniphier-smpctrl"; 207 reg = <0x59801000 0x400>; 208 }; 209 210 syscon@59810000 { 211 compatible = "socionext,uniphier-ld4-mioctrl", 212 "simple-mfd", "syscon"; 213 reg = <0x59810000 0x800>; 214 215 mio_clk: clock-controller { 216 compatible = "socionext,uniphier-ld4-mio-clock"; 217 #clock-cells = <1>; 218 }; 219 220 mio_rst: reset-controller { 221 compatible = "socionext,uniphier-ld4-mio-reset"; 222 #reset-cells = <1>; 223 }; 224 }; 225 226 syscon@59820000 { 227 compatible = "socionext,uniphier-ld4-perictrl", 228 "simple-mfd", "syscon"; 229 reg = <0x59820000 0x200>; 230 231 peri_clk: clock-controller { 232 compatible = "socionext,uniphier-ld4-peri-clock"; 233 #clock-cells = <1>; 234 }; 235 236 peri_rst: reset-controller { 237 compatible = "socionext,uniphier-ld4-peri-reset"; 238 #reset-cells = <1>; 239 }; 240 }; 241 242 dmac: dma-controller@5a000000 { 243 compatible = "socionext,uniphier-mio-dmac"; 244 reg = <0x5a000000 0x1000>; 245 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&mio_clk 7>; 253 resets = <&mio_rst 7>; 254 #dma-cells = <1>; 255 }; 256 257 sd: mmc@5a400000 { 258 compatible = "socionext,uniphier-sd-v2.91"; 259 status = "disabled"; 260 reg = <0x5a400000 0x200>; 261 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 262 pinctrl-names = "default", "uhs"; 263 pinctrl-0 = <&pinctrl_sd>; 264 pinctrl-1 = <&pinctrl_sd_uhs>; 265 clocks = <&mio_clk 0>; 266 reset-names = "host", "bridge"; 267 resets = <&mio_rst 0>, <&mio_rst 3>; 268 dma-names = "rx-tx"; 269 dmas = <&dmac 4>; 270 bus-width = <4>; 271 cap-sd-highspeed; 272 sd-uhs-sdr12; 273 sd-uhs-sdr25; 274 sd-uhs-sdr50; 275 }; 276 277 emmc: mmc@5a500000 { 278 compatible = "socionext,uniphier-sd-v2.91"; 279 status = "disabled"; 280 reg = <0x5a500000 0x200>; 281 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_emmc>; 284 clocks = <&mio_clk 1>; 285 reset-names = "host", "bridge", "hw"; 286 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; 287 dma-names = "rx-tx"; 288 dmas = <&dmac 6>; 289 bus-width = <8>; 290 cap-mmc-highspeed; 291 cap-mmc-hw-reset; 292 non-removable; 293 }; 294 295 usb0: usb@5a800100 { 296 compatible = "socionext,uniphier-ehci", "generic-ehci"; 297 status = "disabled"; 298 reg = <0x5a800100 0x100>; 299 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_usb0>; 302 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 303 <&mio_clk 12>; 304 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 305 <&mio_rst 12>; 306 has-transaction-translator; 307 }; 308 309 usb1: usb@5a810100 { 310 compatible = "socionext,uniphier-ehci", "generic-ehci"; 311 status = "disabled"; 312 reg = <0x5a810100 0x100>; 313 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_usb1>; 316 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 317 <&mio_clk 13>; 318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 319 <&mio_rst 13>; 320 has-transaction-translator; 321 }; 322 323 usb2: usb@5a820100 { 324 compatible = "socionext,uniphier-ehci", "generic-ehci"; 325 status = "disabled"; 326 reg = <0x5a820100 0x100>; 327 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_usb2>; 330 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 331 <&mio_clk 14>; 332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 333 <&mio_rst 14>; 334 has-transaction-translator; 335 }; 336 337 syscon@5f800000 { 338 compatible = "socionext,uniphier-ld4-soc-glue", 339 "simple-mfd", "syscon"; 340 reg = <0x5f800000 0x2000>; 341 342 pinctrl: pinctrl { 343 compatible = "socionext,uniphier-ld4-pinctrl"; 344 }; 345 }; 346 347 syscon@5f900000 { 348 compatible = "socionext,uniphier-ld4-soc-glue-debug", 349 "simple-mfd", "syscon"; 350 reg = <0x5f900000 0x2000>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0 0x5f900000 0x2000>; 354 355 efuse@100 { 356 compatible = "socionext,uniphier-efuse"; 357 reg = <0x100 0x28>; 358 }; 359 360 efuse@130 { 361 compatible = "socionext,uniphier-efuse"; 362 reg = <0x130 0x8>; 363 }; 364 }; 365 366 timer@60000200 { 367 compatible = "arm,cortex-a9-global-timer"; 368 reg = <0x60000200 0x20>; 369 interrupts = <GIC_PPI 11 370 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 371 clocks = <&arm_timer_clk>; 372 }; 373 374 timer@60000600 { 375 compatible = "arm,cortex-a9-twd-timer"; 376 reg = <0x60000600 0x20>; 377 interrupts = <GIC_PPI 13 378 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>; 379 clocks = <&arm_timer_clk>; 380 }; 381 382 intc: interrupt-controller@60001000 { 383 compatible = "arm,cortex-a9-gic"; 384 reg = <0x60001000 0x1000>, 385 <0x60000100 0x100>; 386 #interrupt-cells = <3>; 387 interrupt-controller; 388 }; 389 390 aidet: interrupt-controller@61830000 { 391 compatible = "socionext,uniphier-ld4-aidet"; 392 reg = <0x61830000 0x200>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 syscon@61840000 { 398 compatible = "socionext,uniphier-ld4-sysctrl", 399 "simple-mfd", "syscon"; 400 reg = <0x61840000 0x10000>; 401 402 sys_clk: clock-controller { 403 compatible = "socionext,uniphier-ld4-clock"; 404 #clock-cells = <1>; 405 }; 406 407 sys_rst: reset-controller { 408 compatible = "socionext,uniphier-ld4-reset"; 409 #reset-cells = <1>; 410 }; 411 }; 412 413 nand: nand-controller@68000000 { 414 compatible = "socionext,uniphier-denali-nand-v5a"; 415 status = "disabled"; 416 reg-names = "nand_data", "denali_reg"; 417 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_nand>; 423 clock-names = "nand", "nand_x", "ecc"; 424 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 425 reset-names = "nand", "reg"; 426 resets = <&sys_rst 2>, <&sys_rst 2>; 427 }; 428 }; 429}; 430 431#include "uniphier-pinctrl.dtsi" 432