1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
3 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
4 
5 /*
6  * OMAP2/3 SDRC/SMS macros and prototypes
7  *
8  * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9  * Copyright (C) 2007-2008 Nokia Corporation
10  *
11  * Paul Walmsley
12  * Tony Lindgren
13  * Richard Woodruff
14  */
15 #undef DEBUG
16 
17 #ifndef __ASSEMBLER__
18 
19 #include <linux/io.h>
20 
21 extern void __iomem *omap2_sdrc_base;
22 extern void __iomem *omap2_sms_base;
23 
24 #define OMAP_SDRC_REGADDR(reg)			(omap2_sdrc_base + (reg))
25 #define OMAP_SMS_REGADDR(reg)			(omap2_sms_base + (reg))
26 
27 /* SDRC global register get/set */
28 
sdrc_write_reg(u32 val,u16 reg)29 static inline void sdrc_write_reg(u32 val, u16 reg)
30 {
31 	writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
32 }
33 
sdrc_read_reg(u16 reg)34 static inline u32 sdrc_read_reg(u16 reg)
35 {
36 	return readl_relaxed(OMAP_SDRC_REGADDR(reg));
37 }
38 
39 /* SMS global register get/set */
40 
sms_write_reg(u32 val,u16 reg)41 static inline void sms_write_reg(u32 val, u16 reg)
42 {
43 	writel_relaxed(val, OMAP_SMS_REGADDR(reg));
44 }
45 
sms_read_reg(u16 reg)46 static inline u32 sms_read_reg(u16 reg)
47 {
48 	return readl_relaxed(OMAP_SMS_REGADDR(reg));
49 }
50 
51 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
52 
53 
54 /**
55  * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
56  * @rate: SDRC clock rate (in Hz)
57  * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
58  * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
59  * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
60  * @mr: Value to program to SDRC_MR for this rate
61  *
62  * This structure holds a pre-computed set of register values for the
63  * SDRC for a given SDRC clock rate and SDRAM chip.  These are
64  * intended to be pre-computed and specified in an array in the board-*.c
65  * files.  The structure is keyed off the 'rate' field.
66  */
67 struct omap_sdrc_params {
68 	unsigned long rate;
69 	u32 actim_ctrla;
70 	u32 actim_ctrlb;
71 	u32 rfr_ctrl;
72 	u32 mr;
73 };
74 
75 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
76 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
77 			    struct omap_sdrc_params *sdrc_cs1);
78 #else
omap2_sdrc_init(struct omap_sdrc_params * sdrc_cs0,struct omap_sdrc_params * sdrc_cs1)79 static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
80 					  struct omap_sdrc_params *sdrc_cs1) {};
81 #endif
82 
83 void omap2_sms_restore_context(void);
84 
85 struct memory_timings {
86 	u32 m_type;		/* ddr = 1, sdr = 0 */
87 	u32 dll_mode;		/* use lock mode = 1, unlock mode = 0 */
88 	u32 slow_dll_ctrl;	/* unlock mode, dll value for slow speed */
89 	u32 fast_dll_ctrl;	/* unlock mode, dll value for fast speed */
90 	u32 base_cs;		/* base chip select to use for calculations */
91 };
92 
93 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
94 
95 u32 omap2xxx_sdrc_dll_is_unlocked(void);
96 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
97 
98 
99 #else
100 #define OMAP242X_SDRC_REGADDR(reg)					\
101 			OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
102 #define OMAP243X_SDRC_REGADDR(reg)					\
103 			OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
104 #define OMAP34XX_SDRC_REGADDR(reg)					\
105 			OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
106 
107 #endif	/* __ASSEMBLER__ */
108 
109 /* Minimum frequency that the SDRC DLL can lock at */
110 #define MIN_SDRC_DLL_LOCK_FREQ		83000000
111 
112 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
113 #define SDRC_MPURATE_SCALE		8
114 
115 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
116 #define SDRC_MPURATE_BASE_SHIFT		9
117 
118 /*
119  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
120  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
121  */
122 #define SDRC_MPURATE_LOOPS		96
123 
124 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
125 
126 #define SDRC_SYSCONFIG		0x010
127 #define SDRC_CS_CFG		0x040
128 #define SDRC_SHARING		0x044
129 #define SDRC_ERR_TYPE		0x04C
130 #define SDRC_DLLA_CTRL		0x060
131 #define SDRC_DLLA_STATUS	0x064
132 #define SDRC_DLLB_CTRL		0x068
133 #define SDRC_DLLB_STATUS	0x06C
134 #define SDRC_POWER		0x070
135 #define SDRC_MCFG_0		0x080
136 #define SDRC_MR_0		0x084
137 #define SDRC_EMR2_0		0x08c
138 #define SDRC_ACTIM_CTRL_A_0	0x09c
139 #define SDRC_ACTIM_CTRL_B_0	0x0a0
140 #define SDRC_RFR_CTRL_0		0x0a4
141 #define SDRC_MANUAL_0		0x0a8
142 #define SDRC_MCFG_1		0x0B0
143 #define SDRC_MR_1		0x0B4
144 #define SDRC_EMR2_1		0x0BC
145 #define SDRC_ACTIM_CTRL_A_1	0x0C4
146 #define SDRC_ACTIM_CTRL_B_1	0x0C8
147 #define SDRC_RFR_CTRL_1		0x0D4
148 #define SDRC_MANUAL_1		0x0D8
149 
150 #define SDRC_POWER_AUTOCOUNT_SHIFT	8
151 #define SDRC_POWER_AUTOCOUNT_MASK	(0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
152 #define SDRC_POWER_CLKCTRL_SHIFT	4
153 #define SDRC_POWER_CLKCTRL_MASK		(0x3 << SDRC_POWER_CLKCTRL_SHIFT)
154 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT	(0x2 << SDRC_POWER_CLKCTRL_SHIFT)
155 
156 /*
157  * These values represent the number of memory clock cycles between
158  * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
159  * rows per device, and include a subtraction of a 50 cycle window in the
160  * event that the autorefresh command is delayed due to other SDRC activity.
161  * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
162  * counter reaches 0.
163  *
164  * These represent optimal values for common parts, it won't work for all.
165  * As long as you scale down, most parameters are still work, they just
166  * become sub-optimal. The RFR value goes in the opposite direction. If you
167  * don't adjust it down as your clock period increases the refresh interval
168  * will not be met. Setting all parameters for complete worst case may work,
169  * but may cut memory performance by 2x. Due to errata the DLLs need to be
170  * unlocked and their value needs run time calibration. A dynamic call is
171  * need for that as no single right value exists across production samples.
172  *
173  * Only the FULL speed values are given. Current code is such that rate
174  * changes must be made at DPLLoutx2. The actual value adjustment for low
175  * frequency operation will be handled by omap_set_performance()
176  *
177  * By having the boot loader boot up in the fastest L4 speed available likely
178  * will result in something which you can switch between.
179  */
180 #define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
181 #define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
182 #define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
183 #define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
184 #define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
185 
186 
187 /*
188  * SMS register access
189  */
190 
191 #define OMAP242X_SMS_REGADDR(reg)					\
192 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
193 #define OMAP243X_SMS_REGADDR(reg)					\
194 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
195 #define OMAP343X_SMS_REGADDR(reg)					\
196 		(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
197 
198 /* SMS register offsets - read/write with sms_{read,write}_reg() */
199 
200 #define SMS_SYSCONFIG			0x010
201 /* REVISIT: fill in other SMS registers here */
202 
203 
204 
205 #endif
206