1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/stratix10-clock.h> 10 11/ { 12 compatible = "altr,socfpga-stratix10"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,armv8-pmuv3"; 64 interrupts = <0 170 4>, 65 <0 171 4>, 66 <0 172 4>, 67 <0 173 4>; 68 interrupt-affinity = <&cpu0>, 69 <&cpu1>, 70 <&cpu2>, 71 <&cpu3>; 72 interrupt-parent = <&intc>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 /* Local timer */ 81 timer { 82 compatible = "arm,armv8-timer"; 83 interrupts = <1 13 0xf08>, 84 <1 14 0xf08>, 85 <1 11 0xf08>, 86 <1 10 0xf08>; 87 interrupt-parent = <&intc>; 88 }; 89 90 intc: interrupt-controller@fffc1000 { 91 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 92 #interrupt-cells = <3>; 93 interrupt-controller; 94 reg = <0x0 0xfffc1000 0x0 0x1000>, 95 <0x0 0xfffc2000 0x0 0x2000>, 96 <0x0 0xfffc4000 0x0 0x2000>, 97 <0x0 0xfffc6000 0x0 0x2000>; 98 }; 99 100 clocks { 101 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 102 #clock-cells = <0>; 103 compatible = "fixed-clock"; 104 }; 105 106 cb_intosc_ls_clk: cb-intosc-ls-clk { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 }; 110 111 f2s_free_clk: f2s-free-clk { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 }; 115 116 osc1: osc1 { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 }; 120 121 qspi_clk: qspi-clk { 122 #clock-cells = <0>; 123 compatible = "fixed-clock"; 124 clock-frequency = <200000000>; 125 }; 126 }; 127 128 soc { 129 #address-cells = <1>; 130 #size-cells = <1>; 131 compatible = "simple-bus"; 132 device_type = "soc"; 133 interrupt-parent = <&intc>; 134 ranges = <0 0 0 0xffffffff>; 135 136 base_fpga_region { 137 #address-cells = <0x2>; 138 #size-cells = <0x2>; 139 compatible = "fpga-region"; 140 fpga-mgr = <&fpga_mgr>; 141 }; 142 143 clkmgr: clock-controller@ffd10000 { 144 compatible = "intel,stratix10-clkmgr"; 145 reg = <0xffd10000 0x1000>; 146 #clock-cells = <1>; 147 }; 148 149 gmac0: ethernet@ff800000 { 150 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 151 reg = <0xff800000 0x2000>; 152 interrupts = <0 90 4>; 153 interrupt-names = "macirq"; 154 mac-address = [00 00 00 00 00 00]; 155 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 156 reset-names = "stmmaceth", "stmmaceth-ocp"; 157 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 158 clock-names = "stmmaceth", "ptp_ref"; 159 tx-fifo-depth = <16384>; 160 rx-fifo-depth = <16384>; 161 snps,multicast-filter-bins = <256>; 162 iommus = <&smmu 1>; 163 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 164 status = "disabled"; 165 }; 166 167 gmac1: ethernet@ff802000 { 168 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 169 reg = <0xff802000 0x2000>; 170 interrupts = <0 91 4>; 171 interrupt-names = "macirq"; 172 mac-address = [00 00 00 00 00 00]; 173 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 174 reset-names = "stmmaceth", "stmmaceth-ocp"; 175 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 176 clock-names = "stmmaceth", "ptp_ref"; 177 tx-fifo-depth = <16384>; 178 rx-fifo-depth = <16384>; 179 snps,multicast-filter-bins = <256>; 180 iommus = <&smmu 2>; 181 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 182 status = "disabled"; 183 }; 184 185 gmac2: ethernet@ff804000 { 186 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 187 reg = <0xff804000 0x2000>; 188 interrupts = <0 92 4>; 189 interrupt-names = "macirq"; 190 mac-address = [00 00 00 00 00 00]; 191 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 192 reset-names = "stmmaceth", "stmmaceth-ocp"; 193 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 194 clock-names = "stmmaceth", "ptp_ref"; 195 tx-fifo-depth = <16384>; 196 rx-fifo-depth = <16384>; 197 snps,multicast-filter-bins = <256>; 198 iommus = <&smmu 3>; 199 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 200 status = "disabled"; 201 }; 202 203 gpio0: gpio@ffc03200 { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 compatible = "snps,dw-apb-gpio"; 207 reg = <0xffc03200 0x100>; 208 resets = <&rst GPIO0_RESET>; 209 status = "disabled"; 210 211 porta: gpio-controller@0 { 212 compatible = "snps,dw-apb-gpio-port"; 213 gpio-controller; 214 #gpio-cells = <2>; 215 ngpios = <24>; 216 reg = <0>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 interrupts = <0 110 4>; 220 }; 221 }; 222 223 gpio1: gpio@ffc03300 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "snps,dw-apb-gpio"; 227 reg = <0xffc03300 0x100>; 228 resets = <&rst GPIO1_RESET>; 229 status = "disabled"; 230 231 portb: gpio-controller@0 { 232 compatible = "snps,dw-apb-gpio-port"; 233 gpio-controller; 234 #gpio-cells = <2>; 235 ngpios = <24>; 236 reg = <0>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 interrupts = <0 111 4>; 240 }; 241 }; 242 243 i2c0: i2c@ffc02800 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "snps,designware-i2c"; 247 reg = <0xffc02800 0x100>; 248 interrupts = <0 103 4>; 249 resets = <&rst I2C0_RESET>; 250 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 251 status = "disabled"; 252 }; 253 254 i2c1: i2c@ffc02900 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 compatible = "snps,designware-i2c"; 258 reg = <0xffc02900 0x100>; 259 interrupts = <0 104 4>; 260 resets = <&rst I2C1_RESET>; 261 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 262 status = "disabled"; 263 }; 264 265 i2c2: i2c@ffc02a00 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "snps,designware-i2c"; 269 reg = <0xffc02a00 0x100>; 270 interrupts = <0 105 4>; 271 resets = <&rst I2C2_RESET>; 272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 273 status = "disabled"; 274 }; 275 276 i2c3: i2c@ffc02b00 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "snps,designware-i2c"; 280 reg = <0xffc02b00 0x100>; 281 interrupts = <0 106 4>; 282 resets = <&rst I2C3_RESET>; 283 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 284 status = "disabled"; 285 }; 286 287 i2c4: i2c@ffc02c00 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "snps,designware-i2c"; 291 reg = <0xffc02c00 0x100>; 292 interrupts = <0 107 4>; 293 resets = <&rst I2C4_RESET>; 294 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 295 status = "disabled"; 296 }; 297 298 mmc: mmc@ff808000 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "altr,socfpga-dw-mshc"; 302 reg = <0xff808000 0x1000>; 303 interrupts = <0 96 4>; 304 fifo-depth = <0x400>; 305 resets = <&rst SDMMC_RESET>; 306 reset-names = "reset"; 307 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 308 <&clkmgr STRATIX10_SDMMC_CLK>; 309 clock-names = "biu", "ciu"; 310 iommus = <&smmu 5>; 311 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 312 status = "disabled"; 313 }; 314 315 nand: nand-controller@ffb90000 { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 compatible = "altr,socfpga-denali-nand"; 319 reg = <0xffb90000 0x10000>, 320 <0xffb80000 0x1000>; 321 reg-names = "nand_data", "denali_reg"; 322 interrupts = <0 97 4>; 323 clocks = <&clkmgr STRATIX10_NAND_CLK>, 324 <&clkmgr STRATIX10_NAND_X_CLK>, 325 <&clkmgr STRATIX10_NAND_ECC_CLK>; 326 clock-names = "nand", "nand_x", "ecc"; 327 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 328 status = "disabled"; 329 }; 330 331 ocram: sram@ffe00000 { 332 compatible = "mmio-sram"; 333 reg = <0xffe00000 0x100000>; 334 }; 335 336 pdma: dma-controller@ffda0000 { 337 compatible = "arm,pl330", "arm,primecell"; 338 reg = <0xffda0000 0x1000>; 339 interrupts = <0 81 4>, 340 <0 82 4>, 341 <0 83 4>, 342 <0 84 4>, 343 <0 85 4>, 344 <0 86 4>, 345 <0 87 4>, 346 <0 88 4>, 347 <0 89 4>; 348 #dma-cells = <1>; 349 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 350 clock-names = "apb_pclk"; 351 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 352 reset-names = "dma", "dma-ocp"; 353 }; 354 355 pinctrl0: pinctrl@ffd13000 { 356 compatible = "pinctrl-single"; 357 reg = <0xffd13000 0xA0>; 358 #pinctrl-cells = <1>; 359 pinctrl-single,register-width = <32>; 360 pinctrl-single,function-mask = <0x0000000f>; 361 }; 362 363 pinctrl1: pinctrl@ffd13100 { 364 compatible = "pinctrl-single"; 365 reg = <0xffd13100 0x20>; 366 #pinctrl-cells = <1>; 367 pinctrl-single,register-width = <32>; 368 pinctrl-single,function-mask = <0x0000000f>; 369 }; 370 371 rst: rstmgr@ffd11000 { 372 #reset-cells = <1>; 373 compatible = "altr,stratix10-rst-mgr"; 374 reg = <0xffd11000 0x1000>; 375 }; 376 377 smmu: iommu@fa000000 { 378 compatible = "arm,mmu-500", "arm,smmu-v2"; 379 reg = <0xfa000000 0x40000>; 380 #global-interrupts = <2>; 381 #iommu-cells = <1>; 382 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 383 clock-names = "iommu"; 384 interrupt-parent = <&intc>; 385 interrupts = <0 128 4>, /* Global Secure Fault */ 386 <0 129 4>, /* Global Non-secure Fault */ 387 /* Non-secure Context Interrupts (32) */ 388 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 389 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 390 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 391 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 392 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 393 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 394 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 395 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 396 stream-match-mask = <0x7ff0>; 397 status = "disabled"; 398 }; 399 400 spi0: spi@ffda4000 { 401 compatible = "snps,dw-apb-ssi"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0xffda4000 0x1000>; 405 interrupts = <0 99 4>; 406 resets = <&rst SPIM0_RESET>; 407 reset-names = "spi"; 408 reg-io-width = <4>; 409 num-cs = <4>; 410 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 411 status = "disabled"; 412 }; 413 414 spi1: spi@ffda5000 { 415 compatible = "snps,dw-apb-ssi"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <0xffda5000 0x1000>; 419 interrupts = <0 100 4>; 420 resets = <&rst SPIM1_RESET>; 421 reset-names = "spi"; 422 reg-io-width = <4>; 423 num-cs = <4>; 424 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 425 status = "disabled"; 426 }; 427 428 sysmgr: sysmgr@ffd12000 { 429 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 430 reg = <0xffd12000 0x228>; 431 }; 432 433 timer0: timer0@ffc03000 { 434 compatible = "snps,dw-apb-timer"; 435 interrupts = <0 113 4>; 436 reg = <0xffc03000 0x100>; 437 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 438 clock-names = "timer"; 439 }; 440 441 timer1: timer1@ffc03100 { 442 compatible = "snps,dw-apb-timer"; 443 interrupts = <0 114 4>; 444 reg = <0xffc03100 0x100>; 445 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 446 clock-names = "timer"; 447 }; 448 449 timer2: timer2@ffd00000 { 450 compatible = "snps,dw-apb-timer"; 451 interrupts = <0 115 4>; 452 reg = <0xffd00000 0x100>; 453 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 454 clock-names = "timer"; 455 }; 456 457 timer3: timer3@ffd00100 { 458 compatible = "snps,dw-apb-timer"; 459 interrupts = <0 116 4>; 460 reg = <0xffd00100 0x100>; 461 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 462 clock-names = "timer"; 463 }; 464 465 uart0: serial@ffc02000 { 466 compatible = "snps,dw-apb-uart"; 467 reg = <0xffc02000 0x100>; 468 interrupts = <0 108 4>; 469 reg-shift = <2>; 470 reg-io-width = <4>; 471 resets = <&rst UART0_RESET>; 472 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 473 status = "disabled"; 474 }; 475 476 uart1: serial@ffc02100 { 477 compatible = "snps,dw-apb-uart"; 478 reg = <0xffc02100 0x100>; 479 interrupts = <0 109 4>; 480 reg-shift = <2>; 481 reg-io-width = <4>; 482 resets = <&rst UART1_RESET>; 483 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 484 status = "disabled"; 485 }; 486 487 usbphy0: usbphy@0 { 488 #phy-cells = <0>; 489 compatible = "usb-nop-xceiv"; 490 status = "okay"; 491 }; 492 493 usb0: usb@ffb00000 { 494 compatible = "snps,dwc2"; 495 reg = <0xffb00000 0x40000>; 496 interrupts = <0 93 4>; 497 phys = <&usbphy0>; 498 phy-names = "usb2-phy"; 499 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 500 reset-names = "dwc2", "dwc2-ecc"; 501 clocks = <&clkmgr STRATIX10_USB_CLK>; 502 clock-names = "otg"; 503 iommus = <&smmu 6>; 504 status = "disabled"; 505 }; 506 507 usb1: usb@ffb40000 { 508 compatible = "snps,dwc2"; 509 reg = <0xffb40000 0x40000>; 510 interrupts = <0 94 4>; 511 phys = <&usbphy0>; 512 phy-names = "usb2-phy"; 513 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 514 reset-names = "dwc2", "dwc2-ecc"; 515 clocks = <&clkmgr STRATIX10_USB_CLK>; 516 iommus = <&smmu 7>; 517 status = "disabled"; 518 }; 519 520 watchdog0: watchdog@ffd00200 { 521 compatible = "snps,dw-wdt"; 522 reg = <0xffd00200 0x100>; 523 interrupts = <0 117 4>; 524 resets = <&rst WATCHDOG0_RESET>; 525 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 526 status = "disabled"; 527 }; 528 529 watchdog1: watchdog@ffd00300 { 530 compatible = "snps,dw-wdt"; 531 reg = <0xffd00300 0x100>; 532 interrupts = <0 118 4>; 533 resets = <&rst WATCHDOG1_RESET>; 534 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 535 status = "disabled"; 536 }; 537 538 watchdog2: watchdog@ffd00400 { 539 compatible = "snps,dw-wdt"; 540 reg = <0xffd00400 0x100>; 541 interrupts = <0 125 4>; 542 resets = <&rst WATCHDOG2_RESET>; 543 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 544 status = "disabled"; 545 }; 546 547 watchdog3: watchdog@ffd00500 { 548 compatible = "snps,dw-wdt"; 549 reg = <0xffd00500 0x100>; 550 interrupts = <0 126 4>; 551 resets = <&rst WATCHDOG3_RESET>; 552 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 553 status = "disabled"; 554 }; 555 556 sdr: sdr@f8011100 { 557 compatible = "altr,sdr-ctl", "syscon"; 558 reg = <0xf8011100 0xc0>; 559 }; 560 561 eccmgr { 562 compatible = "altr,socfpga-s10-ecc-manager", 563 "altr,socfpga-a10-ecc-manager"; 564 altr,sysmgr-syscon = <&sysmgr>; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 interrupts = <0 15 4>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 ranges; 571 572 sdramedac { 573 compatible = "altr,sdram-edac-s10"; 574 altr,sdr-syscon = <&sdr>; 575 interrupts = <16 4>; 576 }; 577 578 ocram-ecc@ff8cc000 { 579 compatible = "altr,socfpga-s10-ocram-ecc", 580 "altr,socfpga-a10-ocram-ecc"; 581 reg = <0xff8cc000 0x100>; 582 altr,ecc-parent = <&ocram>; 583 interrupts = <1 4>; 584 }; 585 586 usb0-ecc@ff8c4000 { 587 compatible = "altr,socfpga-s10-usb-ecc", 588 "altr,socfpga-usb-ecc"; 589 reg = <0xff8c4000 0x100>; 590 altr,ecc-parent = <&usb0>; 591 interrupts = <2 4>; 592 }; 593 594 emac0-rx-ecc@ff8c0000 { 595 compatible = "altr,socfpga-s10-eth-mac-ecc", 596 "altr,socfpga-eth-mac-ecc"; 597 reg = <0xff8c0000 0x100>; 598 altr,ecc-parent = <&gmac0>; 599 interrupts = <4 4>; 600 }; 601 602 emac0-tx-ecc@ff8c0400 { 603 compatible = "altr,socfpga-s10-eth-mac-ecc", 604 "altr,socfpga-eth-mac-ecc"; 605 reg = <0xff8c0400 0x100>; 606 altr,ecc-parent = <&gmac0>; 607 interrupts = <5 4>; 608 }; 609 610 }; 611 612 qspi: spi@ff8d2000 { 613 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 reg = <0xff8d2000 0x100>, 617 <0xff900000 0x100000>; 618 interrupts = <0 3 4>; 619 cdns,fifo-depth = <128>; 620 cdns,fifo-width = <4>; 621 cdns,trigger-address = <0x00000000>; 622 clocks = <&qspi_clk>; 623 624 status = "disabled"; 625 }; 626 627 firmware { 628 svc { 629 compatible = "intel,stratix10-svc"; 630 method = "smc"; 631 memory-region = <&service_reserved>; 632 633 fpga_mgr: fpga-mgr { 634 compatible = "intel,stratix10-soc-fpga-mgr"; 635 }; 636 }; 637 }; 638 }; 639}; 640