1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11	aliases {
12		ethernet1 = &eth1;
13		usb0 = &usbotg1;
14		usb1 = &usbotg2;
15	};
16
17	led-controller {
18		compatible = "gpio-leds";
19		pinctrl-names = "default";
20		pinctrl-0 = <&pinctrl_gpio_leds>;
21
22		led-0 {
23			function = LED_FUNCTION_STATUS;
24			color = <LED_COLOR_ID_GREEN>;
25			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26			default-state = "on";
27			linux,default-trigger = "heartbeat";
28		};
29
30		led-1 {
31			function = LED_FUNCTION_STATUS;
32			color = <LED_COLOR_ID_RED>;
33			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34			default-state = "off";
35		};
36	};
37
38	pcie0_refclk: pcie0-refclk {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		clock-frequency = <100000000>;
42	};
43
44	pps {
45		compatible = "pps-gpio";
46		pinctrl-names = "default";
47		pinctrl-0 = <&pinctrl_pps>;
48		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49		status = "okay";
50	};
51
52	reg_1p8v: regulator-1p8v {
53		compatible = "regulator-fixed";
54		regulator-name = "1P8V";
55		regulator-min-microvolt = <1800000>;
56		regulator-max-microvolt = <1800000>;
57		regulator-always-on;
58	};
59
60	reg_3p3v: regulator-3p3v {
61		compatible = "regulator-fixed";
62		regulator-name = "3P3V";
63		regulator-min-microvolt = <3300000>;
64		regulator-max-microvolt = <3300000>;
65		regulator-always-on;
66	};
67
68	reg_usb_otg1_vbus: regulator-usb-otg1 {
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_reg_usb1_en>;
71		compatible = "regulator-fixed";
72		regulator-name = "usb_otg1_vbus";
73		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
74		enable-active-high;
75		regulator-min-microvolt = <5000000>;
76		regulator-max-microvolt = <5000000>;
77	};
78
79	reg_usb_otg2_vbus: regulator-usb-otg2 {
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_reg_usb2_en>;
82		compatible = "regulator-fixed";
83		regulator-name = "usb_otg2_vbus";
84		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
85		enable-active-high;
86		regulator-min-microvolt = <5000000>;
87		regulator-max-microvolt = <5000000>;
88	};
89
90	reg_wifi_en: regulator-wifi-en {
91		pinctrl-names = "default";
92		pinctrl-0 = <&pinctrl_reg_wl>;
93		compatible = "regulator-fixed";
94		regulator-name = "wl";
95		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
96		startup-delay-us = <100>;
97		enable-active-high;
98		regulator-min-microvolt = <3300000>;
99		regulator-max-microvolt = <3300000>;
100	};
101};
102
103/* off-board header */
104&ecspi2 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_spi2>;
107	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
108	status = "okay";
109};
110
111&gpio1 {
112	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
113		"", "", "pci_usb_sel", "dio0",
114		"", "dio1", "", "", "", "", "", "",
115		"", "", "", "", "", "", "", "",
116		"", "", "", "", "", "", "", "";
117};
118
119&gpio4 {
120	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
121		"mipi_gpio1", "", "", "pci_wdis#",
122		"", "", "", "", "", "", "", "",
123		"", "", "", "", "", "", "", "",
124		"", "", "", "", "", "", "", "";
125};
126
127&i2c2 {
128	clock-frequency = <400000>;
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_i2c2>;
131	status = "okay";
132
133	accelerometer@19 {
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_accel>;
136		compatible = "st,lis2de12";
137		reg = <0x19>;
138		st,drdy-int-pin = <1>;
139		interrupt-parent = <&gpio4>;
140		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
141		interrupt-names = "INT1";
142	};
143};
144
145/* off-board header */
146&i2c3 {
147	clock-frequency = <400000>;
148	pinctrl-names = "default";
149	pinctrl-0 = <&pinctrl_i2c3>;
150	status = "okay";
151};
152
153&pcie_phy {
154	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
155	fsl,clkreq-unsupported;
156	clocks = <&pcie0_refclk>;
157	clock-names = "ref";
158	status = "okay";
159};
160
161&pcie0 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_pcie0>;
164	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
165	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
166		 <&clk IMX8MM_CLK_PCIE1_AUX>;
167	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
168			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
169	assigned-clock-rates = <10000000>, <250000000>;
170	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
171				 <&clk IMX8MM_SYS_PLL2_250M>;
172	status = "okay";
173
174	pcie@0,0 {
175		reg = <0x0000 0 0 0 0>;
176		#address-cells = <1>;
177		#size-cells = <0>;
178
179		pcie@1,0 {
180			reg = <0x0000 0 0 0 0>;
181			#address-cells = <1>;
182			#size-cells = <0>;
183
184			pcie@2,4 {
185				reg = <0x2000 0 0 0 0>;
186				#address-cells = <1>;
187				#size-cells = <0>;
188
189				eth1: pcie@6,0 {
190					reg = <0x0000 0 0 0 0>;
191					#address-cells = <1>;
192					#size-cells = <0>;
193
194					local-mac-address = [00 00 00 00 00 00];
195				};
196			};
197		};
198	};
199};
200
201/* off-board header */
202&sai3 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_sai3>;
205	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
206	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
207	assigned-clock-rates = <24576000>;
208	status = "okay";
209};
210
211/* GPS */
212&uart1 {
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_uart1>;
215	status = "okay";
216};
217
218/* bluetooth HCI */
219&uart3 {
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
222	cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
223	rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
224	status = "okay";
225
226	bluetooth {
227		compatible = "brcm,bcm4330-bt";
228		shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
229	};
230};
231
232/* RS232 */
233&uart4 {
234	pinctrl-names = "default";
235	pinctrl-0 = <&pinctrl_uart4>;
236	status = "okay";
237};
238
239&usbotg1 {
240	dr_mode = "otg";
241	over-current-active-low;
242	vbus-supply = <&reg_usb_otg1_vbus>;
243	status = "okay";
244};
245
246&usbotg2 {
247	dr_mode = "host";
248	disable-over-current;
249	vbus-supply = <&reg_usb_otg2_vbus>;
250	status = "okay";
251};
252
253/* SDIO WiFi */
254&usdhc1 {
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_usdhc1>;
257	bus-width = <4>;
258	non-removable;
259	vmmc-supply = <&reg_wifi_en>;
260	status = "okay";
261};
262
263/* microSD */
264&usdhc2 {
265	pinctrl-names = "default", "state_100mhz", "state_200mhz";
266	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
267	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
268	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
269	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
270	bus-width = <4>;
271	vmmc-supply = <&reg_3p3v>;
272	status = "okay";
273};
274
275&iomuxc {
276	pinctrl-names = "default";
277	pinctrl-0 = <&pinctrl_hog>;
278
279	pinctrl_hog: hoggrp {
280		fsl,pins = <
281			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
282			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
283			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
284			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
285			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
286			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */
287			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */
288			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */
289		>;
290	};
291
292	pinctrl_accel: accelgrp {
293		fsl,pins = <
294			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
295		>;
296	};
297
298	pinctrl_bten: btengrp {
299		fsl,pins = <
300			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
301		>;
302	};
303
304	pinctrl_gpio_leds: gpioledgrp {
305		fsl,pins = <
306			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
307			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
308		>;
309	};
310
311	pinctrl_i2c3: i2c3grp {
312		fsl,pins = <
313			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
314			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
315		>;
316	};
317
318	pinctrl_pcie0: pcie0grp {
319		fsl,pins = <
320			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
321		>;
322	};
323
324	pinctrl_pps: ppsgrp {
325		fsl,pins = <
326			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
327		>;
328	};
329
330	pinctrl_reg_wl: regwlgrp {
331		fsl,pins = <
332			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x41
333		>;
334	};
335
336	pinctrl_reg_usb1_en: regusb1grp {
337		fsl,pins = <
338			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
339			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
340		>;
341	};
342
343	pinctrl_reg_usb2_en: regusb2grp {
344		fsl,pins = <
345			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41
346		>;
347	};
348
349	pinctrl_sai3: sai3grp {
350		fsl,pins = <
351			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
352			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
353			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
354			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
355			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
356		>;
357	};
358
359	pinctrl_spi2: spi2grp {
360		fsl,pins = <
361			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
362			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
363			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
364			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
365		>;
366	};
367
368	pinctrl_uart1: uart1grp {
369		fsl,pins = <
370			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
371			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
372		>;
373	};
374
375	pinctrl_uart3: uart3grp {
376		fsl,pins = <
377			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
378			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
379			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x140
380			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140
381		>;
382	};
383
384	pinctrl_uart4: uart4grp {
385		fsl,pins = <
386			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
387			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
388		>;
389	};
390
391	pinctrl_usdhc1: usdhc1grp {
392		fsl,pins = <
393			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
394			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
395			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
396			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
397			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
398			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
399		>;
400	};
401
402	pinctrl_usdhc2: usdhc2grp {
403		fsl,pins = <
404			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
405			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
406			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
407			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
408			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
409			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
410		>;
411	};
412
413	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
414		fsl,pins = <
415			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
416			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
417			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
418			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
419			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
420			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
421		>;
422	};
423
424	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
425		fsl,pins = <
426			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
427			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
428			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
429			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
430			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
431			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
432		>;
433	};
434
435	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
436		fsl,pins = <
437			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
438			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0
439			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
440		>;
441	};
442};
443