1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy-imx8-pcie.h>
13
14#include "imx8mm.dtsi"
15
16/ {
17	model = "Gateworks Venice GW7902 i.MX8MM board";
18	compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19
20	aliases {
21		ethernet1 = &eth1;
22		usb0 = &usbotg1;
23		usb1 = &usbotg2;
24	};
25
26	chosen {
27		stdout-path = &uart2;
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0 0x80000000>;
33	};
34
35	can20m: can20m {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <20000000>;
39		clock-output-names = "can20m";
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		key-user-pb {
46			label = "user_pb";
47			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48			linux,code = <BTN_0>;
49		};
50
51		key-user-pb1x {
52			label = "user_pb1x";
53			linux,code = <BTN_1>;
54			interrupt-parent = <&gsc>;
55			interrupts = <0>;
56		};
57
58		key-erased {
59			label = "key_erased";
60			linux,code = <BTN_2>;
61			interrupt-parent = <&gsc>;
62			interrupts = <1>;
63		};
64
65		key-eeprom-wp {
66			label = "eeprom_wp";
67			linux,code = <BTN_3>;
68			interrupt-parent = <&gsc>;
69			interrupts = <2>;
70		};
71
72		key-tamper {
73			label = "tamper";
74			linux,code = <BTN_4>;
75			interrupt-parent = <&gsc>;
76			interrupts = <5>;
77		};
78
79		switch-hold {
80			label = "switch_hold";
81			linux,code = <BTN_5>;
82			interrupt-parent = <&gsc>;
83			interrupts = <7>;
84		};
85	};
86
87	led-controller {
88		compatible = "gpio-leds";
89		pinctrl-names = "default";
90		pinctrl-0 = <&pinctrl_gpio_leds>;
91
92		led-0 {
93			function = LED_FUNCTION_STATUS;
94			color = <LED_COLOR_ID_GREEN>;
95			label = "panel1";
96			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97			default-state = "off";
98		};
99
100		led-1 {
101			function = LED_FUNCTION_STATUS;
102			color = <LED_COLOR_ID_GREEN>;
103			label = "panel2";
104			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105			default-state = "off";
106		};
107
108		led-2 {
109			function = LED_FUNCTION_STATUS;
110			color = <LED_COLOR_ID_GREEN>;
111			label = "panel3";
112			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113			default-state = "off";
114		};
115
116		led-3 {
117			function = LED_FUNCTION_STATUS;
118			color = <LED_COLOR_ID_GREEN>;
119			label = "panel4";
120			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121			default-state = "off";
122		};
123
124		led-4 {
125			function = LED_FUNCTION_STATUS;
126			color = <LED_COLOR_ID_GREEN>;
127			label = "panel5";
128			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129			default-state = "off";
130		};
131	};
132
133	pcie0_refclk: pcie0-refclk {
134		compatible = "fixed-clock";
135		#clock-cells = <0>;
136		clock-frequency = <100000000>;
137	};
138
139	pps {
140		compatible = "pps-gpio";
141		pinctrl-names = "default";
142		pinctrl-0 = <&pinctrl_pps>;
143		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144		status = "okay";
145	};
146
147	reg_3p3v: regulator-3p3v {
148		compatible = "regulator-fixed";
149		regulator-name = "3P3V";
150		regulator-min-microvolt = <3300000>;
151		regulator-max-microvolt = <3300000>;
152		regulator-always-on;
153	};
154
155	reg_usb1_vbus: regulator-usb1 {
156		compatible = "regulator-fixed";
157		pinctrl-names = "default";
158		pinctrl-0 = <&pinctrl_reg_usb1>;
159		regulator-name = "usb_usb1_vbus";
160		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161		enable-active-high;
162		regulator-min-microvolt = <5000000>;
163		regulator-max-microvolt = <5000000>;
164	};
165
166	reg_wifi: regulator-wifi {
167		compatible = "regulator-fixed";
168		pinctrl-names = "default";
169		pinctrl-0 = <&pinctrl_reg_wl>;
170		regulator-name = "wifi";
171		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172		enable-active-high;
173		startup-delay-us = <100>;
174		regulator-min-microvolt = <3300000>;
175		regulator-max-microvolt = <3300000>;
176	};
177};
178
179&A53_0 {
180	cpu-supply = <&buck2>;
181};
182
183&A53_1 {
184	cpu-supply = <&buck2>;
185};
186
187&A53_2 {
188	cpu-supply = <&buck2>;
189};
190
191&A53_3 {
192	cpu-supply = <&buck2>;
193};
194
195&ddrc {
196	operating-points-v2 = <&ddrc_opp_table>;
197
198	ddrc_opp_table: opp-table {
199		compatible = "operating-points-v2";
200
201		opp-25000000 {
202			opp-hz = /bits/ 64 <25000000>;
203		};
204
205		opp-100000000 {
206			opp-hz = /bits/ 64 <100000000>;
207		};
208
209		opp-750000000 {
210			opp-hz = /bits/ 64 <750000000>;
211		};
212	};
213};
214
215&ecspi1 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_spi1>;
218	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219	status = "okay";
220
221	can@0 {
222		compatible = "microchip,mcp2515";
223		reg = <0>;
224		clocks = <&can20m>;
225		interrupt-parent = <&gpio2>;
226		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227		spi-max-frequency = <10000000>;
228	};
229};
230
231/* off-board header */
232&ecspi2 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_spi2>;
235	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236	status = "okay";
237};
238
239&fec1 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_fec1>;
242	phy-mode = "rgmii-id";
243	phy-handle = <&ethphy0>;
244	local-mac-address = [00 00 00 00 00 00];
245	status = "okay";
246
247	mdio {
248		#address-cells = <1>;
249		#size-cells = <0>;
250
251		ethphy0: ethernet-phy@0 {
252			compatible = "ethernet-phy-ieee802.3-c22";
253			reg = <0>;
254			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258		};
259	};
260};
261
262&gpio1 {
263	gpio-line-names = "", "", "", "", "", "", "", "",
264		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
265		"", "", "", "", "", "", "", "",
266		"", "", "", "", "", "", "", "";
267};
268
269&gpio2 {
270	gpio-line-names = "", "", "", "", "", "", "", "",
271		"uart2_en#", "", "", "", "", "", "", "",
272		"", "", "", "", "", "", "", "",
273		"", "", "", "", "", "", "", "";
274};
275
276&gpio3 {
277	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278		"", "", "", "", "", "", "", "",
279		"", "", "", "", "", "", "", "",
280		"", "", "", "", "", "", "", "";
281};
282
283&gpio4 {
284	gpio-line-names = "", "", "", "", "", "", "", "",
285		"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286		"lte_pwr#", "lte_rst", "lte_int", "",
287		"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
288		"", "uart1_term", "uart1_half", "app_gpio2",
289		"mipi_gpio1", "", "", "";
290};
291
292&gpio5 {
293	gpio-line-names = "", "", "", "mipi_gpio4",
294		"mipi_gpio3", "mipi_gpio2", "", "",
295		"", "", "", "", "", "", "", "",
296		"", "", "", "", "", "", "", "",
297		"", "", "", "", "", "", "", "";
298};
299
300&i2c1 {
301	clock-frequency = <100000>;
302	pinctrl-names = "default", "gpio";
303	pinctrl-0 = <&pinctrl_i2c1>;
304	pinctrl-1 = <&pinctrl_i2c1_gpio>;
305	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
307	status = "okay";
308
309	gsc: gsc@20 {
310		compatible = "gw,gsc";
311		reg = <0x20>;
312		pinctrl-0 = <&pinctrl_gsc>;
313		interrupt-parent = <&gpio2>;
314		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
315		interrupt-controller;
316		#interrupt-cells = <1>;
317
318		adc {
319			compatible = "gw,gsc-adc";
320			#address-cells = <1>;
321			#size-cells = <0>;
322
323			channel@6 {
324				gw,mode = <0>;
325				reg = <0x06>;
326				label = "temp";
327			};
328
329			channel@8 {
330				gw,mode = <1>;
331				reg = <0x08>;
332				label = "vdd_bat";
333			};
334
335			channel@82 {
336				gw,mode = <2>;
337				reg = <0x82>;
338				label = "vin";
339				gw,voltage-divider-ohms = <22100 1000>;
340				gw,voltage-offset-microvolt = <700000>;
341			};
342
343			channel@84 {
344				gw,mode = <2>;
345				reg = <0x84>;
346				label = "vin_4p0";
347				gw,voltage-divider-ohms = <10000 10000>;
348			};
349
350			channel@86 {
351				gw,mode = <2>;
352				reg = <0x86>;
353				label = "vdd_3p3";
354				gw,voltage-divider-ohms = <10000 10000>;
355			};
356
357			channel@88 {
358				gw,mode = <2>;
359				reg = <0x88>;
360				label = "vdd_0p9";
361			};
362
363			channel@8c {
364				gw,mode = <2>;
365				reg = <0x8c>;
366				label = "vdd_soc";
367			};
368
369			channel@8e {
370				gw,mode = <2>;
371				reg = <0x8e>;
372				label = "vdd_arm";
373			};
374
375			channel@90 {
376				gw,mode = <2>;
377				reg = <0x90>;
378				label = "vdd_1p8";
379			};
380
381			channel@92 {
382				gw,mode = <2>;
383				reg = <0x92>;
384				label = "vdd_dram";
385			};
386
387			channel@98 {
388				gw,mode = <2>;
389				reg = <0x98>;
390				label = "vdd_1p0";
391			};
392
393			channel@9a {
394				gw,mode = <2>;
395				reg = <0x9a>;
396				label = "vdd_2p5";
397				gw,voltage-divider-ohms = <10000 10000>;
398			};
399
400			channel@9c {
401				gw,mode = <2>;
402				reg = <0x9c>;
403				label = "vdd_5p0";
404				gw,voltage-divider-ohms = <10000 10000>;
405			};
406
407			channel@a2 {
408				gw,mode = <2>;
409				reg = <0xa2>;
410				label = "vdd_gsc";
411				gw,voltage-divider-ohms = <10000 10000>;
412			};
413		};
414	};
415
416	gpio: gpio@23 {
417		compatible = "nxp,pca9555";
418		reg = <0x23>;
419		gpio-controller;
420		#gpio-cells = <2>;
421		interrupt-parent = <&gsc>;
422		interrupts = <4>;
423	};
424
425	pmic@4b {
426		compatible = "rohm,bd71847";
427		reg = <0x4b>;
428		pinctrl-names = "default";
429		pinctrl-0 = <&pinctrl_pmic>;
430		interrupt-parent = <&gpio3>;
431		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
432		rohm,reset-snvs-powered;
433		#clock-cells = <0>;
434		clocks = <&osc_32k 0>;
435		clock-output-names = "clk-32k-out";
436
437		regulators {
438			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
439			BUCK1 {
440				regulator-name = "buck1";
441				regulator-min-microvolt = <700000>;
442				regulator-max-microvolt = <1300000>;
443				regulator-boot-on;
444				regulator-always-on;
445				regulator-ramp-delay = <1250>;
446			};
447
448			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
449			buck2: BUCK2 {
450				regulator-name = "buck2";
451				regulator-min-microvolt = <700000>;
452				regulator-max-microvolt = <1300000>;
453				regulator-boot-on;
454				regulator-always-on;
455				regulator-ramp-delay = <1250>;
456				rohm,dvs-run-voltage = <1000000>;
457				rohm,dvs-idle-voltage = <900000>;
458			};
459
460			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
461			BUCK3 {
462				regulator-name = "buck3";
463				regulator-min-microvolt = <700000>;
464				regulator-max-microvolt = <1350000>;
465				regulator-boot-on;
466				regulator-always-on;
467			};
468
469			/* vdd_3p3 */
470			BUCK4 {
471				regulator-name = "buck4";
472				regulator-min-microvolt = <3000000>;
473				regulator-max-microvolt = <3300000>;
474				regulator-boot-on;
475				regulator-always-on;
476			};
477
478			/* vdd_1p8 */
479			BUCK5 {
480				regulator-name = "buck5";
481				regulator-min-microvolt = <1605000>;
482				regulator-max-microvolt = <1995000>;
483				regulator-boot-on;
484				regulator-always-on;
485			};
486
487			/* vdd_dram */
488			BUCK6 {
489				regulator-name = "buck6";
490				regulator-min-microvolt = <800000>;
491				regulator-max-microvolt = <1400000>;
492				regulator-boot-on;
493				regulator-always-on;
494			};
495
496			/* nvcc_snvs_1p8 */
497			LDO1 {
498				regulator-name = "ldo1";
499				regulator-min-microvolt = <1600000>;
500				regulator-max-microvolt = <1900000>;
501				regulator-boot-on;
502				regulator-always-on;
503			};
504
505			/* vdd_snvs_0p8 */
506			LDO2 {
507				regulator-name = "ldo2";
508				regulator-min-microvolt = <800000>;
509				regulator-max-microvolt = <900000>;
510				regulator-boot-on;
511				regulator-always-on;
512			};
513
514			/* vdda_1p8 */
515			LDO3 {
516				regulator-name = "ldo3";
517				regulator-min-microvolt = <1800000>;
518				regulator-max-microvolt = <3300000>;
519				regulator-boot-on;
520				regulator-always-on;
521			};
522
523			LDO4 {
524				regulator-name = "ldo4";
525				regulator-min-microvolt = <900000>;
526				regulator-max-microvolt = <1800000>;
527				regulator-boot-on;
528				regulator-always-on;
529			};
530
531			LDO6 {
532				regulator-name = "ldo6";
533				regulator-min-microvolt = <900000>;
534				regulator-max-microvolt = <1800000>;
535				regulator-boot-on;
536				regulator-always-on;
537			};
538		};
539	};
540
541	eeprom@50 {
542		compatible = "atmel,24c02";
543		reg = <0x50>;
544		pagesize = <16>;
545	};
546
547	eeprom@51 {
548		compatible = "atmel,24c02";
549		reg = <0x51>;
550		pagesize = <16>;
551	};
552
553	eeprom@52 {
554		compatible = "atmel,24c02";
555		reg = <0x52>;
556		pagesize = <16>;
557	};
558
559	eeprom@53 {
560		compatible = "atmel,24c02";
561		reg = <0x53>;
562		pagesize = <16>;
563	};
564
565	rtc@68 {
566		compatible = "dallas,ds1672";
567		reg = <0x68>;
568	};
569};
570
571&i2c2 {
572	clock-frequency = <400000>;
573	pinctrl-names = "default", "gpio";
574	pinctrl-0 = <&pinctrl_i2c2>;
575	pinctrl-1 = <&pinctrl_i2c2_gpio>;
576	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
578	status = "okay";
579
580	accelerometer@19 {
581		compatible = "st,lis2de12";
582		pinctrl-names = "default";
583		pinctrl-0 = <&pinctrl_accel>;
584		reg = <0x19>;
585		st,drdy-int-pin = <1>;
586		interrupt-parent = <&gpio1>;
587		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
588		interrupt-names = "INT1";
589	};
590};
591
592/* off-board header */
593&i2c3 {
594	clock-frequency = <400000>;
595	pinctrl-names = "default", "gpio";
596	pinctrl-0 = <&pinctrl_i2c3>;
597	pinctrl-1 = <&pinctrl_i2c3_gpio>;
598	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
599	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
600	status = "okay";
601};
602
603/* off-board header */
604&i2c4 {
605	clock-frequency = <400000>;
606	pinctrl-names = "default", "gpio";
607	pinctrl-0 = <&pinctrl_i2c4>;
608	pinctrl-1 = <&pinctrl_i2c4_gpio>;
609	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
610	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
611	status = "okay";
612};
613
614&pcie_phy {
615	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
616	fsl,clkreq-unsupported;
617	clocks = <&pcie0_refclk>;
618	clock-names = "ref";
619	status = "okay";
620};
621
622&pcie0 {
623	pinctrl-names = "default";
624	pinctrl-0 = <&pinctrl_pcie0>;
625	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
626	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
627		 <&clk IMX8MM_CLK_PCIE1_AUX>;
628	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
629			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
630	assigned-clock-rates = <10000000>, <250000000>;
631	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
632				 <&clk IMX8MM_SYS_PLL2_250M>;
633	status = "okay";
634
635	pcie@0,0 {
636		reg = <0x0000 0 0 0 0>;
637		#address-cells = <1>;
638		#size-cells = <0>;
639
640		eth1: pcie@1,0 {
641			reg = <0x0000 0 0 0 0>;
642			#address-cells = <1>;
643			#size-cells = <0>;
644
645			local-mac-address = [00 00 00 00 00 00];
646		};
647	};
648};
649
650/* off-board header */
651&sai3 {
652	pinctrl-names = "default";
653	pinctrl-0 = <&pinctrl_sai3>;
654	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
655	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
656	assigned-clock-rates = <24576000>;
657	status = "okay";
658};
659
660/* RS232/RS485/RS422 selectable */
661&uart1 {
662	pinctrl-names = "default";
663	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
664	rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
665	cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
666	status = "okay";
667};
668
669/* RS232 console */
670&uart2 {
671	pinctrl-names = "default";
672	pinctrl-0 = <&pinctrl_uart2>;
673	status = "okay";
674};
675
676/* bluetooth HCI */
677&uart3 {
678	pinctrl-names = "default";
679	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
680	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
681	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
682	status = "okay";
683
684	bluetooth {
685		compatible = "brcm,bcm4330-bt";
686		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
687	};
688};
689
690/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
691&uart4 {
692	pinctrl-names = "default";
693	pinctrl-0 = <&pinctrl_uart4>;
694	rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
695	cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
696	dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
697	dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
698	dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
699	status = "okay";
700};
701
702&usbotg1 {
703	dr_mode = "host";
704	vbus-supply = <&reg_usb1_vbus>;
705	disable-over-current;
706	status = "okay";
707};
708
709&usbotg2 {
710	dr_mode = "host";
711	disable-over-current;
712	status = "okay";
713};
714
715/* SDIO WiFi */
716&usdhc2 {
717	pinctrl-names = "default";
718	pinctrl-0 = <&pinctrl_usdhc2>;
719	bus-width = <4>;
720	non-removable;
721	vmmc-supply = <&reg_wifi>;
722	status = "okay";
723};
724
725/* eMMC */
726&usdhc3 {
727	pinctrl-names = "default", "state_100mhz", "state_200mhz";
728	pinctrl-0 = <&pinctrl_usdhc3>;
729	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
730	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
731	bus-width = <8>;
732	non-removable;
733	status = "okay";
734};
735
736&wdog1 {
737	pinctrl-names = "default";
738	pinctrl-0 = <&pinctrl_wdog>;
739	fsl,ext-reset-output;
740	status = "okay";
741};
742
743&iomuxc {
744	pinctrl-names = "default";
745	pinctrl-0 = <&pinctrl_hog>;
746
747	pinctrl_hog: hoggrp {
748		fsl,pins = <
749			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
750			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */
751			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
752			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
753			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
754			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x40000041 /* LTE_INT */
755			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17       0x40000041 /* LTE_RST# */
756			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x40000041 /* LTE_PWR */
757			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */
758			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */
759			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */
760			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */
761			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
762			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */
763			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
764			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
765			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
766			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
767			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
768			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
769		>;
770	};
771
772	pinctrl_accel: accelgrp {
773		fsl,pins = <
774			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
775		>;
776	};
777
778	pinctrl_fec1: fec1grp {
779		fsl,pins = <
780			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
781			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
782			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
783			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
784			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
785			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
786			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
787			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
788			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
789			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
790			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
791			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
792			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
793			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
794			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
795			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
796		>;
797	};
798
799	pinctrl_gsc: gscgrp {
800		fsl,pins = <
801			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
802		>;
803	};
804
805	pinctrl_i2c1: i2c1grp {
806		fsl,pins = <
807			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
808			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
809		>;
810	};
811
812	pinctrl_i2c1_gpio: i2c1gpiogrp {
813		fsl,pins = <
814			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
815			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
816		>;
817	};
818
819	pinctrl_i2c2: i2c2grp {
820		fsl,pins = <
821			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
822			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
823		>;
824	};
825
826	pinctrl_i2c2_gpio: i2c2gpiogrp {
827		fsl,pins = <
828			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
829			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
830		>;
831	};
832
833	pinctrl_i2c3: i2c3grp {
834		fsl,pins = <
835			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
836			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
837		>;
838	};
839
840	pinctrl_i2c3_gpio: i2c3gpiogrp {
841		fsl,pins = <
842			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
843			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
844		>;
845	};
846
847	pinctrl_i2c4: i2c4grp {
848		fsl,pins = <
849			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
850			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
851		>;
852	};
853
854	pinctrl_i2c4_gpio: i2c4gpiogrp {
855		fsl,pins = <
856			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
857			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
858		>;
859	};
860
861	pinctrl_gpio_leds: gpioledgrp {
862		fsl,pins = <
863			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
864			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
865			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
866			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
867			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
868		>;
869	};
870
871	pinctrl_pcie0: pciegrp {
872		fsl,pins = <
873			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x41
874		>;
875	};
876
877	pinctrl_pmic: pmicgrp {
878		fsl,pins = <
879			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
880		>;
881	};
882
883	pinctrl_pps: ppsgrp {
884		fsl,pins = <
885			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
886		>;
887	};
888
889	pinctrl_reg_wl: regwlgrp {
890		fsl,pins = <
891			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
892		>;
893	};
894
895	pinctrl_reg_usb1: regusb1grp {
896		fsl,pins = <
897			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
898		>;
899	};
900
901	pinctrl_sai3: sai3grp {
902		fsl,pins = <
903			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
904			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
905			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
906			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
907			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
908		>;
909	};
910
911	pinctrl_spi1: spi1grp {
912		fsl,pins = <
913			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
914			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
915			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
916			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
917			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
918		>;
919	};
920
921	pinctrl_spi2: spi2grp {
922		fsl,pins = <
923			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
924			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
925			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
926			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
927		>;
928	};
929
930	pinctrl_uart1: uart1grp {
931		fsl,pins = <
932			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
933			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
934			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140 /* RTS */
935			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140 /* CTS */
936		>;
937	};
938
939	pinctrl_uart1_gpio: uart1gpiogrp {
940		fsl,pins = <
941			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
942			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
943			MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
944		>;
945	};
946
947	pinctrl_uart2: uart2grp {
948		fsl,pins = <
949			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
950			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
951		>;
952	};
953
954	pinctrl_uart3_gpio: uart3_gpiogrp {
955		fsl,pins = <
956			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
957		>;
958	};
959
960	pinctrl_uart3: uart3grp {
961		fsl,pins = <
962			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
963			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
964			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
965			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
966		>;
967	};
968
969	pinctrl_uart4: uart4grp {
970		fsl,pins = <
971			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
972			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
973			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x140 /* CTS */
974			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x140 /* RTS */
975			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x140 /* DTR */
976			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x140 /* DSR */
977			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x140 /* DCD */
978			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x140 /* RI */
979			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x140 /* GNSS_PPS */
980			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
981		>;
982	};
983
984	pinctrl_usdhc2: usdhc2grp {
985		fsl,pins = <
986			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
987			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
988			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
989			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
990			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
991			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
992		>;
993	};
994
995	pinctrl_usdhc3: usdhc3grp {
996		fsl,pins = <
997			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
998			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
999			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
1000			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
1001			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
1002			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
1003			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
1004			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
1005			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
1006			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
1007			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
1008		>;
1009	};
1010
1011	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1012		fsl,pins = <
1013			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
1014			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
1015			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
1016			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
1017			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
1018			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
1019			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
1020			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
1021			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
1022			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
1023			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
1024		>;
1025	};
1026
1027	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1028		fsl,pins = <
1029			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
1030			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
1031			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
1032			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
1033			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
1034			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
1035			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
1036			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
1037			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
1038			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
1039			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
1040		>;
1041	};
1042
1043	pinctrl_wdog: wdoggrp {
1044		fsl,pins = <
1045			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
1046		>;
1047	};
1048};
1049