1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16	model = "Gateworks Venice GW74xx i.MX8MP board";
17	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
18
19	aliases {
20		ethernet0 = &eqos;
21		ethernet1 = &fec;
22		ethernet2 = &lan1;
23		ethernet3 = &lan2;
24		ethernet4 = &lan3;
25		ethernet5 = &lan4;
26		ethernet6 = &lan5;
27	};
28
29	chosen {
30		stdout-path = &uart2;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0 0x80000000>;
36	};
37
38	gpio-keys {
39		compatible = "gpio-keys";
40
41		key-0 {
42			label = "user_pb";
43			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
44			linux,code = <BTN_0>;
45		};
46
47		key-1 {
48			label = "user_pb1x";
49			linux,code = <BTN_1>;
50			interrupt-parent = <&gsc>;
51			interrupts = <0>;
52		};
53
54		key-2 {
55			label = "key_erased";
56			linux,code = <BTN_2>;
57			interrupt-parent = <&gsc>;
58			interrupts = <1>;
59		};
60
61		key-3 {
62			label = "eeprom_wp";
63			linux,code = <BTN_3>;
64			interrupt-parent = <&gsc>;
65			interrupts = <2>;
66		};
67
68		key-4 {
69			label = "tamper";
70			linux,code = <BTN_4>;
71			interrupt-parent = <&gsc>;
72			interrupts = <5>;
73		};
74
75		key-5 {
76			label = "switch_hold";
77			linux,code = <BTN_5>;
78			interrupt-parent = <&gsc>;
79			interrupts = <7>;
80		};
81	};
82
83	led-controller {
84		compatible = "gpio-leds";
85		pinctrl-names = "default";
86		pinctrl-0 = <&pinctrl_gpio_leds>;
87
88		led-0 {
89			function = LED_FUNCTION_HEARTBEAT;
90			color = <LED_COLOR_ID_GREEN>;
91			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
92			default-state = "on";
93			linux,default-trigger = "heartbeat";
94		};
95
96		led-1 {
97			function = LED_FUNCTION_STATUS;
98			color = <LED_COLOR_ID_RED>;
99			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
100			default-state = "off";
101		};
102	};
103
104	pcie0_refclk: pcie0-refclk {
105		compatible = "fixed-clock";
106		#clock-cells = <0>;
107		clock-frequency = <100000000>;
108	};
109
110	pps {
111		compatible = "pps-gpio";
112		pinctrl-names = "default";
113		pinctrl-0 = <&pinctrl_pps>;
114		gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
115	};
116
117	reg_usb2_vbus: regulator-usb2 {
118		pinctrl-names = "default";
119		pinctrl-0 = <&pinctrl_reg_usb2>;
120		compatible = "regulator-fixed";
121		regulator-name = "usb_usb2_vbus";
122		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
123		enable-active-high;
124		regulator-min-microvolt = <5000000>;
125		regulator-max-microvolt = <5000000>;
126	};
127
128	reg_can2_stby: regulator-can2-stby {
129		compatible = "regulator-fixed";
130		pinctrl-names = "default";
131		pinctrl-0 = <&pinctrl_reg_can>;
132		regulator-name = "can2_stby";
133		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
134		regulator-min-microvolt = <3300000>;
135		regulator-max-microvolt = <3300000>;
136	};
137
138	reg_wifi_en: regulator-wifi-en {
139		pinctrl-names = "default";
140		pinctrl-0 = <&pinctrl_reg_wifi>;
141		compatible = "regulator-fixed";
142		regulator-name = "wl";
143		gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
144		startup-delay-us = <70000>;
145		enable-active-high;
146		regulator-min-microvolt = <3300000>;
147		regulator-max-microvolt = <3300000>;
148	};
149};
150
151&A53_0 {
152	cpu-supply = <&reg_arm>;
153};
154
155&A53_1 {
156	cpu-supply = <&reg_arm>;
157};
158
159&A53_2 {
160	cpu-supply = <&reg_arm>;
161};
162
163&A53_3 {
164	cpu-supply = <&reg_arm>;
165};
166
167/* off-board header */
168&ecspi2 {
169	pinctrl-names = "default";
170	pinctrl-0 = <&pinctrl_spi2>;
171	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
172	status = "okay";
173};
174
175&eqos {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_eqos>;
178	phy-mode = "rgmii-id";
179	phy-handle = <&ethphy0>;
180	status = "okay";
181
182	mdio {
183		compatible = "snps,dwmac-mdio";
184		#address-cells = <1>;
185		#size-cells = <0>;
186
187		ethphy0: ethernet-phy@0 {
188			compatible = "ethernet-phy-ieee802.3-c22";
189			reg = <0x0>;
190		};
191	};
192};
193
194&fec {
195	pinctrl-names = "default";
196	pinctrl-0 = <&pinctrl_fec>;
197	phy-mode = "rgmii-id";
198	local-mac-address = [00 00 00 00 00 00];
199	status = "okay";
200
201	fixed-link {
202		speed = <1000>;
203		full-duplex;
204	};
205};
206
207&flexcan2 {
208	pinctrl-names = "default";
209	pinctrl-0 = <&pinctrl_flexcan2>;
210	xceiver-supply = <&reg_can2_stby>;
211	status = "okay";
212};
213
214&gpio1 {
215	gpio-line-names =
216		"", "", "", "", "", "", "", "",
217		"", "", "dio0", "", "dio1", "", "", "",
218		"", "", "", "", "", "", "", "",
219		"", "", "", "", "", "", "", "";
220};
221
222&gpio2 {
223	gpio-line-names =
224		"", "", "", "", "", "", "", "",
225		"", "", "", "", "", "", "pcie3_wdis#", "",
226		"", "", "pcie2_wdis#", "", "", "", "", "",
227		"", "", "", "", "", "", "", "";
228};
229
230&gpio3 {
231	gpio-line-names =
232		"m2_gdis#", "", "", "", "", "", "", "m2_rst#",
233		"", "", "", "", "", "", "", "",
234		"m2_off#", "", "", "", "", "", "", "",
235		"", "", "", "", "", "", "", "";
236};
237
238&gpio4 {
239	gpio-line-names =
240		"", "", "", "", "", "", "", "",
241		"", "", "", "", "", "", "", "",
242		"", "", "", "", "m2_wdis#", "", "", "",
243		"", "", "", "", "", "", "", "uart_rs485";
244};
245
246&gpio5 {
247	gpio-line-names =
248		"uart_half", "uart_term", "", "", "", "", "", "",
249		"", "", "", "", "", "", "", "",
250		"", "", "", "", "", "", "", "",
251		"", "", "", "", "", "", "", "";
252};
253
254&i2c1 {
255	clock-frequency = <100000>;
256	pinctrl-names = "default", "gpio";
257	pinctrl-0 = <&pinctrl_i2c1>;
258	pinctrl-1 = <&pinctrl_i2c1_gpio>;
259	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
260	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
261	status = "okay";
262
263	gsc: gsc@20 {
264		compatible = "gw,gsc";
265		reg = <0x20>;
266		pinctrl-0 = <&pinctrl_gsc>;
267		interrupt-parent = <&gpio4>;
268		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
269		interrupt-controller;
270		#interrupt-cells = <1>;
271
272		adc {
273			compatible = "gw,gsc-adc";
274			#address-cells = <1>;
275			#size-cells = <0>;
276
277			channel@6 {
278				gw,mode = <0>;
279				reg = <0x06>;
280				label = "temp";
281			};
282
283			channel@8 {
284				gw,mode = <1>;
285				reg = <0x08>;
286				label = "vdd_bat";
287			};
288
289			channel@82 {
290				gw,mode = <2>;
291				reg = <0x82>;
292				label = "vdd_adc1";
293				gw,voltage-divider-ohms = <10000 10000>;
294			};
295
296			channel@84 {
297				gw,mode = <2>;
298				reg = <0x84>;
299				label = "vdd_adc2";
300				gw,voltage-divider-ohms = <10000 10000>;
301			};
302
303			channel@86 {
304				gw,mode = <2>;
305				reg = <0x86>;
306				label = "vdd_vin";
307				gw,voltage-divider-ohms = <22100 1000>;
308			};
309
310			channel@88 {
311				gw,mode = <2>;
312				reg = <0x88>;
313				label = "vdd_3p3";
314				gw,voltage-divider-ohms = <10000 10000>;
315			};
316
317			channel@8c {
318				gw,mode = <2>;
319				reg = <0x8c>;
320				label = "vdd_2p5";
321				gw,voltage-divider-ohms = <10000 10000>;
322			};
323
324			channel@90 {
325				gw,mode = <2>;
326				reg = <0x90>;
327				label = "vdd_soc";
328			};
329
330			channel@92 {
331				gw,mode = <2>;
332				reg = <0x92>;
333				label = "vdd_arm";
334			};
335
336			channel@98 {
337				gw,mode = <2>;
338				reg = <0x98>;
339				label = "vdd_1p8";
340			};
341
342			channel@9a {
343				gw,mode = <2>;
344				reg = <0x9a>;
345				label = "vdd_1p2";
346			};
347
348			channel@9c {
349				gw,mode = <2>;
350				reg = <0x9c>;
351				label = "vdd_dram";
352			};
353
354			channel@a2 {
355				gw,mode = <2>;
356				reg = <0xa2>;
357				label = "vdd_gsc";
358				gw,voltage-divider-ohms = <10000 10000>;
359			};
360		};
361	};
362
363	gpio: gpio@23 {
364		compatible = "nxp,pca9555";
365		reg = <0x23>;
366		gpio-controller;
367		#gpio-cells = <2>;
368		interrupt-parent = <&gsc>;
369		interrupts = <4>;
370	};
371
372	pmic@25 {
373		compatible = "nxp,pca9450c";
374		reg = <0x25>;
375		pinctrl-names = "default";
376		pinctrl-0 = <&pinctrl_pmic>;
377		interrupt-parent = <&gpio3>;
378		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
379
380		regulators {
381			BUCK1 {
382				regulator-name = "BUCK1";
383				regulator-min-microvolt = <720000>;
384				regulator-max-microvolt = <1000000>;
385				regulator-boot-on;
386				regulator-always-on;
387				regulator-ramp-delay = <3125>;
388			};
389
390			reg_arm: BUCK2 {
391				regulator-name = "BUCK2";
392				regulator-min-microvolt = <720000>;
393				regulator-max-microvolt = <1025000>;
394				regulator-boot-on;
395				regulator-always-on;
396				regulator-ramp-delay = <3125>;
397				nxp,dvs-run-voltage = <950000>;
398				nxp,dvs-standby-voltage = <850000>;
399			};
400
401			BUCK4 {
402				regulator-name = "BUCK4";
403				regulator-min-microvolt = <3000000>;
404				regulator-max-microvolt = <3600000>;
405				regulator-boot-on;
406				regulator-always-on;
407			};
408
409			BUCK5 {
410				regulator-name = "BUCK5";
411				regulator-min-microvolt = <1650000>;
412				regulator-max-microvolt = <1950000>;
413				regulator-boot-on;
414				regulator-always-on;
415			};
416
417			BUCK6 {
418				regulator-name = "BUCK6";
419				regulator-min-microvolt = <1045000>;
420				regulator-max-microvolt = <1155000>;
421				regulator-boot-on;
422				regulator-always-on;
423			};
424
425			LDO1 {
426				regulator-name = "LDO1";
427				regulator-min-microvolt = <1650000>;
428				regulator-max-microvolt = <1950000>;
429				regulator-boot-on;
430				regulator-always-on;
431			};
432
433			LDO3 {
434				regulator-name = "LDO3";
435				regulator-min-microvolt = <1710000>;
436				regulator-max-microvolt = <1890000>;
437				regulator-boot-on;
438				regulator-always-on;
439			};
440
441			LDO5 {
442				regulator-name = "LDO5";
443				regulator-min-microvolt = <1800000>;
444				regulator-max-microvolt = <3300000>;
445				regulator-boot-on;
446				regulator-always-on;
447			};
448		};
449	};
450
451	eeprom@50 {
452		compatible = "atmel,24c02";
453		reg = <0x50>;
454		pagesize = <16>;
455	};
456
457	eeprom@51 {
458		compatible = "atmel,24c02";
459		reg = <0x51>;
460		pagesize = <16>;
461	};
462
463	eeprom@52 {
464		compatible = "atmel,24c02";
465		reg = <0x52>;
466		pagesize = <16>;
467	};
468
469	eeprom@53 {
470		compatible = "atmel,24c02";
471		reg = <0x53>;
472		pagesize = <16>;
473	};
474
475	rtc@68 {
476		compatible = "dallas,ds1672";
477		reg = <0x68>;
478	};
479};
480
481&i2c2 {
482	clock-frequency = <400000>;
483	pinctrl-names = "default", "gpio";
484	pinctrl-0 = <&pinctrl_i2c2>;
485	pinctrl-1 = <&pinctrl_i2c2_gpio>;
486	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
487	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
488	status = "okay";
489
490	accelerometer@19 {
491		compatible = "st,lis2de12";
492		pinctrl-names = "default";
493		pinctrl-0 = <&pinctrl_accel>;
494		reg = <0x19>;
495		st,drdy-int-pin = <1>;
496		interrupt-parent = <&gpio1>;
497		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
498		interrupt-names = "INT1";
499	};
500
501	switch: switch@5f {
502		compatible = "microchip,ksz9897";
503		reg = <0x5f>;
504		pinctrl-0 = <&pinctrl_ksz>;
505		interrupt-parent = <&gpio4>;
506		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
507
508		ports {
509			#address-cells = <1>;
510			#size-cells = <0>;
511
512			lan1: port@0 {
513				reg = <0>;
514				label = "lan1";
515				phy-mode = "internal";
516				local-mac-address = [00 00 00 00 00 00];
517			};
518
519			lan2: port@1 {
520				reg = <1>;
521				label = "lan2";
522				phy-mode = "internal";
523				local-mac-address = [00 00 00 00 00 00];
524			};
525
526			lan3: port@2 {
527				reg = <2>;
528				label = "lan3";
529				phy-mode = "internal";
530				local-mac-address = [00 00 00 00 00 00];
531			};
532
533			lan4: port@3 {
534				reg = <3>;
535				label = "lan4";
536				phy-mode = "internal";
537				local-mac-address = [00 00 00 00 00 00];
538			};
539
540			lan5: port@4 {
541				reg = <4>;
542				label = "lan5";
543				phy-mode = "internal";
544				local-mac-address = [00 00 00 00 00 00];
545			};
546
547			port@5 {
548				reg = <5>;
549				label = "cpu";
550				ethernet = <&fec>;
551				phy-mode = "rgmii-id";
552
553				fixed-link {
554					speed = <1000>;
555					full-duplex;
556				};
557			};
558		};
559	};
560};
561
562/* off-board header */
563&i2c3 {
564	clock-frequency = <400000>;
565	pinctrl-names = "default", "gpio";
566	pinctrl-0 = <&pinctrl_i2c3>;
567	pinctrl-1 = <&pinctrl_i2c3_gpio>;
568	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
569	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
570	status = "okay";
571};
572
573/* off-board header */
574&i2c4 {
575	clock-frequency = <400000>;
576	pinctrl-names = "default", "gpio";
577	pinctrl-0 = <&pinctrl_i2c4>;
578	pinctrl-1 = <&pinctrl_i2c4_gpio>;
579	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
580	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
581	status = "okay";
582};
583
584&pcie_phy {
585	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
586	fsl,clkreq-unsupported;
587	clocks = <&pcie0_refclk>;
588	clock-names = "ref";
589	status = "okay";
590};
591
592&pcie {
593	pinctrl-names = "default";
594	pinctrl-0 = <&pinctrl_pcie0>;
595	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
596	status = "okay";
597};
598
599/* GPS / off-board header */
600&uart1 {
601	pinctrl-names = "default";
602	pinctrl-0 = <&pinctrl_uart1>;
603	status = "okay";
604};
605
606/* RS232 console */
607&uart2 {
608	pinctrl-names = "default";
609	pinctrl-0 = <&pinctrl_uart2>;
610	status = "okay";
611};
612
613/* bluetooth HCI */
614&uart3 {
615	pinctrl-names = "default";
616	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
617	cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
618	rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
619	status = "okay";
620
621	bluetooth {
622		compatible = "brcm,bcm4330-bt";
623		shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
624	};
625};
626
627&uart4 {
628	pinctrl-names = "default";
629	pinctrl-0 = <&pinctrl_uart4>;
630	status = "okay";
631};
632
633/* USB1 - Type C front panel */
634&usb3_0 {
635	pinctrl-names = "default";
636	pinctrl-0 = <&pinctrl_usb1>;
637	fsl,over-current-active-low;
638	status = "okay";
639};
640
641&usb3_phy0 {
642	status = "okay";
643};
644
645&usb_dwc3_0 {
646	/* dual role is implemented but not a full featured OTG */
647	adp-disable;
648	hnp-disable;
649	srp-disable;
650	dr_mode = "otg";
651	usb-role-switch;
652	role-switch-default-mode = "peripheral";
653	status = "okay";
654
655	connector {
656		pinctrl-names = "default";
657		pinctrl-0 = <&pinctrl_usbcon1>;
658		compatible = "gpio-usb-b-connector", "usb-b-connector";
659		type = "micro";
660		label = "Type-C";
661		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
662	};
663};
664
665/* USB2 - USB3.0 Hub */
666&usb3_phy1 {
667	vbus-supply = <&reg_usb2_vbus>;
668	status = "okay";
669};
670
671&usb3_1 {
672	fsl,permanently-attached;
673	fsl,disable-port-power-control;
674	status = "okay";
675};
676
677&usb_dwc3_1 {
678	dr_mode = "host";
679	status = "okay";
680};
681
682/* SDIO WiFi */
683&usdhc1 {
684	pinctrl-names = "default", "state_100mhz", "state_200mhz";
685	pinctrl-0 = <&pinctrl_usdhc1>;
686	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
687	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
688	bus-width = <4>;
689	non-removable;
690	vmmc-supply = <&reg_wifi_en>;
691	#address-cells = <1>;
692	#size-cells = <0>;
693	status = "okay";
694
695	wifi@0 {
696		compatible = "cypress,cyw4373-fmac";
697		reg = <0>;
698	};
699};
700
701/* eMMC */
702&usdhc3 {
703	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
704	assigned-clock-rates = <400000000>;
705	pinctrl-names = "default", "state_100mhz", "state_200mhz";
706	pinctrl-0 = <&pinctrl_usdhc3>;
707	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
708	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
709	bus-width = <8>;
710	non-removable;
711	status = "okay";
712};
713
714&wdog1 {
715	pinctrl-names = "default";
716	pinctrl-0 = <&pinctrl_wdog>;
717	fsl,ext-reset-output;
718	status = "okay";
719};
720
721&iomuxc {
722	pinctrl-names = "default";
723	pinctrl-0 = <&pinctrl_hog>;
724
725	pinctrl_hog: hoggrp {
726		fsl,pins = <
727			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */
728			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */
729			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000040 /* M2SKT_OFF# */
730			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */
731			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */
732			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */
733			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */
734			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000150 /* M2SKT_GDIS# */
735			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */
736			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */
737			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
738		>;
739	};
740
741	pinctrl_accel: accelgrp {
742		fsl,pins = <
743			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150
744		>;
745	};
746
747	pinctrl_eqos: eqosgrp {
748		fsl,pins = <
749			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
750			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
751			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
752			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
753			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
754			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
755			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
756			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
757			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
758			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
759			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
760			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
761			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
762			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
763			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */
764			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */
765		>;
766	};
767
768	pinctrl_fec: fecgrp {
769		fsl,pins = <
770			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
771			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
772			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
773			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
774			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
775			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
776			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
777			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
778			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
779			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
780			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
781			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
782			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140
783			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140
784		>;
785	};
786
787	pinctrl_flexcan2: flexcan2grp {
788		fsl,pins = <
789			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
790			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
791		>;
792	};
793
794	pinctrl_gsc: gscgrp {
795		fsl,pins = <
796			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150
797		>;
798	};
799
800	pinctrl_i2c1: i2c1grp {
801		fsl,pins = <
802			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
803			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
804		>;
805	};
806
807	pinctrl_i2c1_gpio: i2c1gpiogrp {
808		fsl,pins = <
809			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
810			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
811		>;
812	};
813
814	pinctrl_i2c2: i2c2grp {
815		fsl,pins = <
816			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
817			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
818		>;
819	};
820
821	pinctrl_i2c2_gpio: i2c2gpiogrp {
822		fsl,pins = <
823			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c3
824			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c3
825		>;
826	};
827
828	pinctrl_i2c3: i2c3grp {
829		fsl,pins = <
830			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
831			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
832		>;
833	};
834
835	pinctrl_i2c3_gpio: i2c3gpiogrp {
836		fsl,pins = <
837			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c3
838			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c3
839		>;
840	};
841
842	pinctrl_i2c4: i2c4grp {
843		fsl,pins = <
844			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2
845			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2
846		>;
847	};
848
849	pinctrl_i2c4_gpio: i2c4gpiogrp {
850		fsl,pins = <
851			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c3
852			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c3
853		>;
854	};
855
856	pinctrl_ksz: kszgrp {
857		fsl,pins = <
858			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */
859			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */
860		>;
861	};
862
863	pinctrl_gpio_leds: ledgrp {
864		fsl,pins = <
865			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10
866			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10
867		>;
868	};
869
870	pinctrl_pcie0: pciegrp {
871		fsl,pins = <
872			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x110
873		>;
874	};
875
876	pinctrl_pmic: pmicgrp {
877		fsl,pins = <
878			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140
879		>;
880	};
881
882	pinctrl_pps: ppsgrp {
883		fsl,pins = <
884			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140
885		>;
886	};
887
888	pinctrl_reg_can: regcangrp {
889		fsl,pins = <
890			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x154
891		>;
892	};
893
894	pinctrl_reg_usb2: regusb2grp {
895		fsl,pins = <
896			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140
897		>;
898	};
899
900	pinctrl_reg_wifi: regwifigrp {
901		fsl,pins = <
902			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110
903		>;
904	};
905
906	pinctrl_sai2: sai2grp {
907		fsl,pins = <
908			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
909			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
910			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
911			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6
912		>;
913	};
914
915	pinctrl_spi2: spi2grp {
916		fsl,pins = <
917			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82
918			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82
919			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82
920			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
921		>;
922	};
923
924	pinctrl_uart1: uart1grp {
925		fsl,pins = <
926			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
927			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
928		>;
929	};
930
931	pinctrl_uart2: uart2grp {
932		fsl,pins = <
933			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
934			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
935		>;
936	};
937
938	pinctrl_uart3: uart3grp {
939		fsl,pins = <
940			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
941			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
942			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140
943			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x140
944		>;
945	};
946
947	pinctrl_uart3_gpio: uart3gpiogrp {
948		fsl,pins = <
949			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110
950		>;
951	};
952
953	pinctrl_uart4: uart4grp {
954		fsl,pins = <
955			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
956			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
957		>;
958	};
959
960	pinctrl_usb1: usb1grp {
961		fsl,pins = <
962			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140
963		>;
964	};
965
966	pinctrl_usbcon1: usb1congrp {
967		fsl,pins = <
968			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140
969		>;
970	};
971
972	pinctrl_usdhc1: usdhc1grp {
973		fsl,pins = <
974			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
975			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
976			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
977			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
978			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
979			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
980		>;
981	};
982
983	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
984		fsl,pins = <
985			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
986			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
987			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
988			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
989			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
990			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
991		>;
992	};
993
994	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
995		fsl,pins = <
996			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
997			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
998			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
999			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
1000			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
1001			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
1002		>;
1003	};
1004
1005	pinctrl_usdhc3: usdhc3grp {
1006		fsl,pins = <
1007			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
1008			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
1009			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
1010			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
1011			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
1012			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
1013			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
1014			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
1015			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
1016			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
1017			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
1018		>;
1019	};
1020
1021	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1022		fsl,pins = <
1023			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
1024			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
1025			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
1026			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
1027			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
1028			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
1029			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
1030			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
1031			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
1032			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
1033			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
1034		>;
1035	};
1036
1037	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1038		fsl,pins = <
1039			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
1040			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
1041			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
1042			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
1043			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
1044			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
1045			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
1046			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
1047			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
1048			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
1049			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
1050		>;
1051	};
1052
1053	pinctrl_wdog: wdoggrp {
1054		fsl,pins = <
1055			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
1056		>;
1057	};
1058};
1059