1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP80x.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/dts-v1/;
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	aliases {
18		serial0 = &uart0;
19		serial1 = &uart1;
20		gpio0 = &ap_gpio;
21		spi0 = &spi0;
22	};
23
24	psci {
25		compatible = "arm,psci-0.2";
26		method = "smc";
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		/*
35		 * This area matches the mapping done with a
36		 * mainline U-Boot, and should be updated by the
37		 * bootloader.
38		 */
39
40		psci-area@4000000 {
41			reg = <0x0 0x4000000 0x0 0x200000>;
42			no-map;
43		};
44
45		tee@4400000 {
46			reg = <0 0x4400000 0 0x1000000>;
47			no-map;
48		};
49	};
50
51	AP_NAME {
52		#address-cells = <2>;
53		#size-cells = <2>;
54		compatible = "simple-bus";
55		interrupt-parent = <&gic>;
56		ranges;
57
58		config-space@f0000000 {
59			#address-cells = <1>;
60			#size-cells = <1>;
61			compatible = "simple-bus";
62			ranges = <0x0 0x0 0xf0000000 0x1000000>;
63
64			smmu: iommu@5000000 {
65				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
66				reg = <0x100000 0x100000>;
67				dma-coherent;
68				#iommu-cells = <1>;
69				#global-interrupts = <1>;
70				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
74					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
75					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
76					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
77					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
79				status = "disabled";
80			};
81
82			gic: interrupt-controller@210000 {
83				compatible = "arm,gic-400";
84				#interrupt-cells = <3>;
85				#address-cells = <1>;
86				#size-cells = <1>;
87				ranges;
88				interrupt-controller;
89				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90				reg = <0x210000 0x10000>,
91				      <0x220000 0x20000>,
92				      <0x240000 0x20000>,
93				      <0x260000 0x20000>;
94
95				gic_v2m0: v2m@280000 {
96					compatible = "arm,gic-v2m-frame";
97					msi-controller;
98					reg = <0x280000 0x1000>;
99					arm,msi-base-spi = <160>;
100					arm,msi-num-spis = <32>;
101				};
102				gic_v2m1: v2m@290000 {
103					compatible = "arm,gic-v2m-frame";
104					msi-controller;
105					reg = <0x290000 0x1000>;
106					arm,msi-base-spi = <192>;
107					arm,msi-num-spis = <32>;
108				};
109				gic_v2m2: v2m@2a0000 {
110					compatible = "arm,gic-v2m-frame";
111					msi-controller;
112					reg = <0x2a0000 0x1000>;
113					arm,msi-base-spi = <224>;
114					arm,msi-num-spis = <32>;
115				};
116				gic_v2m3: v2m@2b0000 {
117					compatible = "arm,gic-v2m-frame";
118					msi-controller;
119					reg = <0x2b0000 0x1000>;
120					arm,msi-base-spi = <256>;
121					arm,msi-num-spis = <32>;
122				};
123			};
124
125			timer {
126				compatible = "arm,armv8-timer";
127				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
130					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
131			};
132
133			pmu {
134				compatible = "arm,cortex-a72-pmu";
135				interrupt-parent = <&pic>;
136				interrupts = <17>;
137			};
138
139			odmi: odmi@300000 {
140				compatible = "marvell,odmi-controller";
141				interrupt-controller;
142				msi-controller;
143				marvell,odmi-frames = <4>;
144				reg = <0x300000 0x4000>,
145				      <0x304000 0x4000>,
146				      <0x308000 0x4000>,
147				      <0x30C000 0x4000>;
148				marvell,spi-base = <128>, <136>, <144>, <152>;
149			};
150
151			gicp: gicp@3f0040 {
152				compatible = "marvell,ap806-gicp";
153				reg = <0x3f0040 0x10>;
154				marvell,spi-ranges = <64 64>, <288 64>;
155				msi-controller;
156			};
157
158			pic: interrupt-controller@3f0100 {
159				compatible = "marvell,armada-8k-pic";
160				reg = <0x3f0100 0x10>;
161				#interrupt-cells = <1>;
162				interrupt-controller;
163				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
164			};
165
166			sei: interrupt-controller@3f0200 {
167				compatible = "marvell,ap806-sei";
168				reg = <0x3f0200 0x40>;
169				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
170				#interrupt-cells = <1>;
171				interrupt-controller;
172				msi-controller;
173			};
174
175			xor@400000 {
176				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
177				reg = <0x400000 0x1000>,
178				      <0x410000 0x1000>;
179				msi-parent = <&gic_v2m0>;
180				clocks = <&ap_clk 3>;
181				dma-coherent;
182			};
183
184			xor@420000 {
185				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
186				reg = <0x420000 0x1000>,
187				      <0x430000 0x1000>;
188				msi-parent = <&gic_v2m0>;
189				clocks = <&ap_clk 3>;
190				dma-coherent;
191			};
192
193			xor@440000 {
194				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
195				reg = <0x440000 0x1000>,
196				      <0x450000 0x1000>;
197				msi-parent = <&gic_v2m0>;
198				clocks = <&ap_clk 3>;
199				dma-coherent;
200			};
201
202			xor@460000 {
203				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
204				reg = <0x460000 0x1000>,
205				      <0x470000 0x1000>;
206				msi-parent = <&gic_v2m0>;
207				clocks = <&ap_clk 3>;
208				dma-coherent;
209			};
210
211			spi0: spi@510600 {
212				compatible = "marvell,armada-380-spi";
213				reg = <0x510600 0x50>;
214				#address-cells = <1>;
215				#size-cells = <0>;
216				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
217				clocks = <&ap_clk 3>;
218				status = "disabled";
219			};
220
221			i2c0: i2c@511000 {
222				compatible = "marvell,mv78230-i2c";
223				reg = <0x511000 0x20>;
224				#address-cells = <1>;
225				#size-cells = <0>;
226				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
227				clocks = <&ap_clk 3>;
228				status = "disabled";
229			};
230
231			uart0: serial@512000 {
232				compatible = "snps,dw-apb-uart";
233				reg = <0x512000 0x100>;
234				reg-shift = <2>;
235				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
236				reg-io-width = <1>;
237				clocks = <&ap_clk 3>;
238				status = "disabled";
239			};
240
241			uart1: serial@512100 {
242				compatible = "snps,dw-apb-uart";
243				reg = <0x512100 0x100>;
244				reg-shift = <2>;
245				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
246				reg-io-width = <1>;
247				clocks = <&ap_clk 3>;
248				status = "disabled";
249
250			};
251
252			watchdog: watchdog@610000 {
253				compatible = "arm,sbsa-gwdt";
254				reg = <0x610000 0x1000>, <0x600000 0x1000>;
255				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
256			};
257
258			ap_sdhci0: mmc@6e0000 {
259				compatible = "marvell,armada-ap806-sdhci";
260				reg = <0x6e0000 0x300>;
261				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
262				clock-names = "core";
263				clocks = <&ap_clk 4>;
264				dma-coherent;
265				marvell,xenon-phy-slow-mode;
266				status = "disabled";
267			};
268
269			ap_syscon0: system-controller@6f4000 {
270				compatible = "syscon", "simple-mfd";
271				reg = <0x6f4000 0x2000>;
272
273				ap_pinctrl: pinctrl {
274					compatible = "marvell,ap806-pinctrl";
275
276					uart0_pins: uart0-pins {
277						marvell,pins = "mpp11", "mpp19";
278						marvell,function = "uart0";
279					};
280				};
281
282				ap_gpio: gpio@1040 {
283					compatible = "marvell,armada-8k-gpio";
284					offset = <0x1040>;
285					ngpios = <20>;
286					gpio-controller;
287					#gpio-cells = <2>;
288					gpio-ranges = <&ap_pinctrl 0 0 20>;
289					marvell,pwm-offset = <0x10c0>;
290					#pwm-cells = <2>;
291					clocks = <&ap_clk 3>;
292				};
293			};
294
295			ap_syscon1: system-controller@6f8000 {
296				compatible = "syscon", "simple-mfd";
297				reg = <0x6f8000 0x1000>;
298				#address-cells = <1>;
299				#size-cells = <1>;
300
301				ap_thermal: thermal-sensor@80 {
302					compatible = "marvell,armada-ap806-thermal";
303					reg = <0x80 0x10>;
304					interrupt-parent = <&sei>;
305					interrupts = <18>;
306					#thermal-sensor-cells = <1>;
307				};
308			};
309		};
310	};
311
312	/*
313	 * The thermal IP features one internal sensor plus, if applicable, one
314	 * remote channel wired to one sensor per CPU.
315	 *
316	 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
317	 * first one that will have a critical trip point will be chosen.
318	 */
319	thermal-zones {
320		ap_thermal_ic: ap-thermal-ic {
321			polling-delay-passive = <0>; /* Interrupt driven */
322			polling-delay = <0>; /* Interrupt driven */
323
324			thermal-sensors = <&ap_thermal 0>;
325
326			trips {
327				ap_crit: ap-crit {
328					temperature = <100000>; /* mC degrees */
329					hysteresis = <2000>; /* mC degrees */
330					type = "critical";
331				};
332			};
333
334			cooling-maps { };
335		};
336
337		ap_thermal_cpu0: ap-thermal-cpu0 {
338			polling-delay-passive = <1000>;
339			polling-delay = <1000>;
340
341			thermal-sensors = <&ap_thermal 1>;
342
343			trips {
344				cpu0_hot: cpu0-hot {
345					temperature = <85000>;
346					hysteresis = <2000>;
347					type = "passive";
348				};
349				cpu0_emerg: cpu0-emerg {
350					temperature = <95000>;
351					hysteresis = <2000>;
352					type = "passive";
353				};
354			};
355
356			cooling-maps {
357				map0_hot: map0-hot {
358					trip = <&cpu0_hot>;
359					cooling-device = <&cpu0 1 2>,
360						<&cpu1 1 2>;
361				};
362				map0_emerg: map0-ermerg {
363					trip = <&cpu0_emerg>;
364					cooling-device = <&cpu0 3 3>,
365						<&cpu1 3 3>;
366				};
367			};
368		};
369
370		ap_thermal_cpu1: ap-thermal-cpu1 {
371			polling-delay-passive = <1000>;
372			polling-delay = <1000>;
373
374			thermal-sensors = <&ap_thermal 2>;
375
376			trips {
377				cpu1_hot: cpu1-hot {
378					temperature = <85000>;
379					hysteresis = <2000>;
380					type = "passive";
381				};
382				cpu1_emerg: cpu1-emerg {
383					temperature = <95000>;
384					hysteresis = <2000>;
385					type = "passive";
386				};
387			};
388
389			cooling-maps {
390				map1_hot: map1-hot {
391					trip = <&cpu1_hot>;
392					cooling-device = <&cpu0 1 2>,
393						<&cpu1 1 2>;
394				};
395				map1_emerg: map1-emerg {
396					trip = <&cpu1_emerg>;
397					cooling-device = <&cpu0 3 3>,
398						<&cpu1 3 3>;
399				};
400			};
401		};
402
403		ap_thermal_cpu2: ap-thermal-cpu2 {
404			polling-delay-passive = <1000>;
405			polling-delay = <1000>;
406
407			thermal-sensors = <&ap_thermal 3>;
408
409			trips {
410				cpu2_hot: cpu2-hot {
411					temperature = <85000>;
412					hysteresis = <2000>;
413					type = "passive";
414				};
415				cpu2_emerg: cpu2-emerg {
416					temperature = <95000>;
417					hysteresis = <2000>;
418					type = "passive";
419				};
420			};
421
422			cooling-maps {
423				map2_hot: map2-hot {
424					trip = <&cpu2_hot>;
425					cooling-device = <&cpu2 1 2>,
426						<&cpu3 1 2>;
427				};
428				map2_emerg: map2-emerg {
429					trip = <&cpu2_emerg>;
430					cooling-device = <&cpu2 3 3>,
431						<&cpu3 3 3>;
432				};
433			};
434		};
435
436		ap_thermal_cpu3: ap-thermal-cpu3 {
437			polling-delay-passive = <1000>;
438			polling-delay = <1000>;
439
440			thermal-sensors = <&ap_thermal 4>;
441
442			trips {
443				cpu3_hot: cpu3-hot {
444					temperature = <85000>;
445					hysteresis = <2000>;
446					type = "passive";
447				};
448				cpu3_emerg: cpu3-emerg {
449					temperature = <95000>;
450					hysteresis = <2000>;
451					type = "passive";
452				};
453			};
454
455			cooling-maps {
456				map3_hot: map3-bhot {
457					trip = <&cpu3_hot>;
458					cooling-device = <&cpu2 1 2>,
459						<&cpu3 1 2>;
460				};
461				map3_emerg: map3-emerg {
462					trip = <&cpu3_emerg>;
463					cooling-device = <&cpu2 3 3>,
464						<&cpu3 3 3>;
465				};
466			};
467		};
468	};
469};
470