1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/mt7622-clk.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/power/mt7622-power.h>
14#include <dt-bindings/reset/mt7622-reset.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	compatible = "mediatek,mt7622";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	cpu_opp_table: opp-table {
24		compatible = "operating-points-v2";
25		opp-shared;
26		opp-300000000 {
27			opp-hz = /bits/ 64 <30000000>;
28			opp-microvolt = <950000>;
29		};
30
31		opp-437500000 {
32			opp-hz = /bits/ 64 <437500000>;
33			opp-microvolt = <1000000>;
34		};
35
36		opp-600000000 {
37			opp-hz = /bits/ 64 <600000000>;
38			opp-microvolt = <1050000>;
39		};
40
41		opp-812500000 {
42			opp-hz = /bits/ 64 <812500000>;
43			opp-microvolt = <1100000>;
44		};
45
46		opp-1025000000 {
47			opp-hz = /bits/ 64 <1025000000>;
48			opp-microvolt = <1150000>;
49		};
50
51		opp-1137500000 {
52			opp-hz = /bits/ 64 <1137500000>;
53			opp-microvolt = <1200000>;
54		};
55
56		opp-1262500000 {
57			opp-hz = /bits/ 64 <1262500000>;
58			opp-microvolt = <1250000>;
59		};
60
61		opp-1350000000 {
62			opp-hz = /bits/ 64 <1350000000>;
63			opp-microvolt = <1310000>;
64		};
65	};
66
67	cpus {
68		#address-cells = <2>;
69		#size-cells = <0>;
70
71		cpu0: cpu@0 {
72			device_type = "cpu";
73			compatible = "arm,cortex-a53";
74			reg = <0x0 0x0>;
75			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77			clock-names = "cpu", "intermediate";
78			operating-points-v2 = <&cpu_opp_table>;
79			#cooling-cells = <2>;
80			enable-method = "psci";
81			clock-frequency = <1300000000>;
82			cci-control-port = <&cci_control2>;
83			next-level-cache = <&L2>;
84		};
85
86		cpu1: cpu@1 {
87			device_type = "cpu";
88			compatible = "arm,cortex-a53";
89			reg = <0x0 0x1>;
90			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92			clock-names = "cpu", "intermediate";
93			operating-points-v2 = <&cpu_opp_table>;
94			#cooling-cells = <2>;
95			enable-method = "psci";
96			clock-frequency = <1300000000>;
97			cci-control-port = <&cci_control2>;
98			next-level-cache = <&L2>;
99		};
100
101		L2: l2-cache {
102			compatible = "cache";
103			cache-level = <2>;
104		};
105	};
106
107	pwrap_clk: dummy40m {
108		compatible = "fixed-clock";
109		clock-frequency = <40000000>;
110		#clock-cells = <0>;
111	};
112
113	clk25m: oscillator {
114		compatible = "fixed-clock";
115		#clock-cells = <0>;
116		clock-frequency = <25000000>;
117		clock-output-names = "clkxtal";
118	};
119
120	psci {
121		compatible = "arm,psci-0.2";
122		method = "smc";
123	};
124
125	pmu {
126		compatible = "arm,cortex-a53-pmu";
127		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
128			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
129		interrupt-affinity = <&cpu0>, <&cpu1>;
130	};
131
132	reserved-memory {
133		#address-cells = <2>;
134		#size-cells = <2>;
135		ranges;
136
137		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
138		secmon_reserved: secmon@43000000 {
139			reg = <0 0x43000000 0 0x30000>;
140			no-map;
141		};
142	};
143
144	thermal-zones {
145		cpu_thermal: cpu-thermal {
146			polling-delay-passive = <1000>;
147			polling-delay = <1000>;
148
149			thermal-sensors = <&thermal 0>;
150
151			trips {
152				cpu_passive: cpu-passive {
153					temperature = <47000>;
154					hysteresis = <2000>;
155					type = "passive";
156				};
157
158				cpu_active: cpu-active {
159					temperature = <67000>;
160					hysteresis = <2000>;
161					type = "active";
162				};
163
164				cpu_hot: cpu-hot {
165					temperature = <87000>;
166					hysteresis = <2000>;
167					type = "hot";
168				};
169
170				cpu-crit {
171					temperature = <107000>;
172					hysteresis = <2000>;
173					type = "critical";
174				};
175			};
176
177			cooling-maps {
178				map0 {
179					trip = <&cpu_passive>;
180					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182				};
183
184				map1 {
185					trip = <&cpu_active>;
186					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
188				};
189
190				map2 {
191					trip = <&cpu_hot>;
192					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194				};
195			};
196		};
197	};
198
199	timer {
200		compatible = "arm,armv8-timer";
201		interrupt-parent = <&gic>;
202		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
203			      IRQ_TYPE_LEVEL_HIGH)>,
204			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
205			      IRQ_TYPE_LEVEL_HIGH)>,
206			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
207			      IRQ_TYPE_LEVEL_HIGH)>,
208			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
209			      IRQ_TYPE_LEVEL_HIGH)>;
210	};
211
212	infracfg: infracfg@10000000 {
213		compatible = "mediatek,mt7622-infracfg",
214			     "syscon";
215		reg = <0 0x10000000 0 0x1000>;
216		#clock-cells = <1>;
217		#reset-cells = <1>;
218	};
219
220	pwrap: pwrap@10001000 {
221		compatible = "mediatek,mt7622-pwrap";
222		reg = <0 0x10001000 0 0x250>;
223		reg-names = "pwrap";
224		clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
225		clock-names = "spi", "wrap";
226		resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
227		reset-names = "pwrap";
228		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
229		status = "disabled";
230	};
231
232	pericfg: pericfg@10002000 {
233		compatible = "mediatek,mt7622-pericfg",
234			     "syscon";
235		reg = <0 0x10002000 0 0x1000>;
236		#clock-cells = <1>;
237		#reset-cells = <1>;
238	};
239
240	scpsys: power-controller@10006000 {
241		compatible = "mediatek,mt7622-scpsys",
242			     "syscon";
243		#power-domain-cells = <1>;
244		reg = <0 0x10006000 0 0x1000>;
245		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
246			     <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
247			     <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
248			     <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
249		infracfg = <&infracfg>;
250		clocks = <&topckgen CLK_TOP_HIF_SEL>;
251		clock-names = "hif_sel";
252	};
253
254	cir: cir@10009000 {
255		compatible = "mediatek,mt7622-cir";
256		reg = <0 0x10009000 0 0x1000>;
257		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
258		clocks = <&infracfg CLK_INFRA_IRRX_PD>,
259			 <&topckgen CLK_TOP_AXI_SEL>;
260		clock-names = "clk", "bus";
261		status = "disabled";
262	};
263
264	sysirq: interrupt-controller@10200620 {
265		compatible = "mediatek,mt7622-sysirq",
266			     "mediatek,mt6577-sysirq";
267		interrupt-controller;
268		#interrupt-cells = <3>;
269		interrupt-parent = <&gic>;
270		reg = <0 0x10200620 0 0x20>;
271	};
272
273	efuse: efuse@10206000 {
274		compatible = "mediatek,mt7622-efuse",
275			     "mediatek,efuse";
276		reg = <0 0x10206000 0 0x1000>;
277		#address-cells = <1>;
278		#size-cells = <1>;
279
280		thermal_calibration: calib@198 {
281			reg = <0x198 0xc>;
282		};
283	};
284
285	apmixedsys: apmixedsys@10209000 {
286		compatible = "mediatek,mt7622-apmixedsys",
287			     "syscon";
288		reg = <0 0x10209000 0 0x1000>;
289		#clock-cells = <1>;
290	};
291
292	topckgen: topckgen@10210000 {
293		compatible = "mediatek,mt7622-topckgen",
294			     "syscon";
295		reg = <0 0x10210000 0 0x1000>;
296		#clock-cells = <1>;
297	};
298
299	rng: rng@1020f000 {
300		compatible = "mediatek,mt7622-rng",
301			     "mediatek,mt7623-rng";
302		reg = <0 0x1020f000 0 0x1000>;
303		clocks = <&infracfg CLK_INFRA_TRNG>;
304		clock-names = "rng";
305	};
306
307	pio: pinctrl@10211000 {
308		compatible = "mediatek,mt7622-pinctrl";
309		reg = <0 0x10211000 0 0x1000>,
310		      <0 0x10005000 0 0x1000>;
311		reg-names = "base", "eint";
312		gpio-controller;
313		#gpio-cells = <2>;
314		gpio-ranges = <&pio 0 0 103>;
315		interrupt-controller;
316		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
317		interrupt-parent = <&gic>;
318		#interrupt-cells = <2>;
319	};
320
321	watchdog: watchdog@10212000 {
322		compatible = "mediatek,mt7622-wdt",
323			     "mediatek,mt6589-wdt";
324		reg = <0 0x10212000 0 0x800>;
325	};
326
327	rtc: rtc@10212800 {
328		compatible = "mediatek,mt7622-rtc",
329			     "mediatek,soc-rtc";
330		reg = <0 0x10212800 0 0x200>;
331		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
332		clocks = <&topckgen CLK_TOP_RTC>;
333		clock-names = "rtc";
334	};
335
336	gic: interrupt-controller@10300000 {
337		compatible = "arm,gic-400";
338		interrupt-controller;
339		#interrupt-cells = <3>;
340		interrupt-parent = <&gic>;
341		reg = <0 0x10310000 0 0x1000>,
342		      <0 0x10320000 0 0x1000>,
343		      <0 0x10340000 0 0x2000>,
344		      <0 0x10360000 0 0x2000>;
345	};
346
347	cci: cci@10390000 {
348		compatible = "arm,cci-400";
349		#address-cells = <1>;
350		#size-cells = <1>;
351		reg = <0 0x10390000 0 0x1000>;
352		ranges = <0 0 0x10390000 0x10000>;
353
354		cci_control0: slave-if@1000 {
355			compatible = "arm,cci-400-ctrl-if";
356			interface-type = "ace-lite";
357			reg = <0x1000 0x1000>;
358		};
359
360		cci_control1: slave-if@4000 {
361			compatible = "arm,cci-400-ctrl-if";
362			interface-type = "ace";
363			reg = <0x4000 0x1000>;
364		};
365
366		cci_control2: slave-if@5000 {
367			compatible = "arm,cci-400-ctrl-if", "syscon";
368			interface-type = "ace";
369			reg = <0x5000 0x1000>;
370		};
371
372		pmu@9000 {
373			compatible = "arm,cci-400-pmu,r1";
374			reg = <0x9000 0x5000>;
375			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
376				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
377				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
378				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
379				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
380		};
381	};
382
383	auxadc: adc@11001000 {
384		compatible = "mediatek,mt7622-auxadc";
385		reg = <0 0x11001000 0 0x1000>;
386		clocks = <&pericfg CLK_PERI_AUXADC_PD>;
387		clock-names = "main";
388		#io-channel-cells = <1>;
389	};
390
391	uart0: serial@11002000 {
392		compatible = "mediatek,mt7622-uart",
393			     "mediatek,mt6577-uart";
394		reg = <0 0x11002000 0 0x400>;
395		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
396		clocks = <&topckgen CLK_TOP_UART_SEL>,
397			 <&pericfg CLK_PERI_UART0_PD>;
398		clock-names = "baud", "bus";
399		status = "disabled";
400	};
401
402	uart1: serial@11003000 {
403		compatible = "mediatek,mt7622-uart",
404			     "mediatek,mt6577-uart";
405		reg = <0 0x11003000 0 0x400>;
406		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
407		clocks = <&topckgen CLK_TOP_UART_SEL>,
408			 <&pericfg CLK_PERI_UART1_PD>;
409		clock-names = "baud", "bus";
410		status = "disabled";
411	};
412
413	uart2: serial@11004000 {
414		compatible = "mediatek,mt7622-uart",
415			     "mediatek,mt6577-uart";
416		reg = <0 0x11004000 0 0x400>;
417		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
418		clocks = <&topckgen CLK_TOP_UART_SEL>,
419			 <&pericfg CLK_PERI_UART2_PD>;
420		clock-names = "baud", "bus";
421		status = "disabled";
422	};
423
424	uart3: serial@11005000 {
425		compatible = "mediatek,mt7622-uart",
426			     "mediatek,mt6577-uart";
427		reg = <0 0x11005000 0 0x400>;
428		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
429		clocks = <&topckgen CLK_TOP_UART_SEL>,
430			 <&pericfg CLK_PERI_UART3_PD>;
431		clock-names = "baud", "bus";
432		status = "disabled";
433	};
434
435	pwm: pwm@11006000 {
436		compatible = "mediatek,mt7622-pwm";
437		reg = <0 0x11006000 0 0x1000>;
438		#pwm-cells = <2>;
439		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
440		clocks = <&topckgen CLK_TOP_PWM_SEL>,
441			 <&pericfg CLK_PERI_PWM_PD>,
442			 <&pericfg CLK_PERI_PWM1_PD>,
443			 <&pericfg CLK_PERI_PWM2_PD>,
444			 <&pericfg CLK_PERI_PWM3_PD>,
445			 <&pericfg CLK_PERI_PWM4_PD>,
446			 <&pericfg CLK_PERI_PWM5_PD>,
447			 <&pericfg CLK_PERI_PWM6_PD>;
448		clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
449			      "pwm5", "pwm6";
450		status = "disabled";
451	};
452
453	i2c0: i2c@11007000 {
454		compatible = "mediatek,mt7622-i2c";
455		reg = <0 0x11007000 0 0x90>,
456		      <0 0x11000100 0 0x80>;
457		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
458		clock-div = <16>;
459		clocks = <&pericfg CLK_PERI_I2C0_PD>,
460			 <&pericfg CLK_PERI_AP_DMA_PD>;
461		clock-names = "main", "dma";
462		#address-cells = <1>;
463		#size-cells = <0>;
464		status = "disabled";
465	};
466
467	i2c1: i2c@11008000 {
468		compatible = "mediatek,mt7622-i2c";
469		reg = <0 0x11008000 0 0x90>,
470		      <0 0x11000180 0 0x80>;
471		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
472		clock-div = <16>;
473		clocks = <&pericfg CLK_PERI_I2C1_PD>,
474			 <&pericfg CLK_PERI_AP_DMA_PD>;
475		clock-names = "main", "dma";
476		#address-cells = <1>;
477		#size-cells = <0>;
478		status = "disabled";
479	};
480
481	i2c2: i2c@11009000 {
482		compatible = "mediatek,mt7622-i2c";
483		reg = <0 0x11009000 0 0x90>,
484		      <0 0x11000200 0 0x80>;
485		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
486		clock-div = <16>;
487		clocks = <&pericfg CLK_PERI_I2C2_PD>,
488			 <&pericfg CLK_PERI_AP_DMA_PD>;
489		clock-names = "main", "dma";
490		#address-cells = <1>;
491		#size-cells = <0>;
492		status = "disabled";
493	};
494
495	spi0: spi@1100a000 {
496		compatible = "mediatek,mt7622-spi";
497		reg = <0 0x1100a000 0 0x100>;
498		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
499		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
500			 <&topckgen CLK_TOP_SPI0_SEL>,
501			 <&pericfg CLK_PERI_SPI0_PD>;
502		clock-names = "parent-clk", "sel-clk", "spi-clk";
503		#address-cells = <1>;
504		#size-cells = <0>;
505		status = "disabled";
506	};
507
508	thermal: thermal@1100b000 {
509		#thermal-sensor-cells = <1>;
510		compatible = "mediatek,mt7622-thermal";
511		reg = <0 0x1100b000 0 0x1000>;
512		interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
513		clocks = <&pericfg CLK_PERI_THERM_PD>,
514			 <&pericfg CLK_PERI_AUXADC_PD>;
515		clock-names = "therm", "auxadc";
516		resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
517		reset-names = "therm";
518		mediatek,auxadc = <&auxadc>;
519		mediatek,apmixedsys = <&apmixedsys>;
520		nvmem-cells = <&thermal_calibration>;
521		nvmem-cell-names = "calibration-data";
522	};
523
524	btif: serial@1100c000 {
525		compatible = "mediatek,mt7622-btif",
526			     "mediatek,mtk-btif";
527		reg = <0 0x1100c000 0 0x1000>;
528		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
529		clocks = <&pericfg CLK_PERI_BTIF_PD>;
530		reg-shift = <2>;
531		reg-io-width = <4>;
532		status = "disabled";
533
534		bluetooth {
535			compatible = "mediatek,mt7622-bluetooth";
536			power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
537			clocks = <&clk25m>;
538			clock-names = "ref";
539		};
540	};
541
542	nandc: nfi@1100d000 {
543		compatible = "mediatek,mt7622-nfc";
544		reg = <0 0x1100D000 0 0x1000>;
545		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
546		clocks = <&pericfg CLK_PERI_NFI_PD>,
547			 <&pericfg CLK_PERI_SNFI_PD>;
548		clock-names = "nfi_clk", "pad_clk";
549		ecc-engine = <&bch>;
550		#address-cells = <1>;
551		#size-cells = <0>;
552		status = "disabled";
553	};
554
555	snfi: spi@1100d000 {
556		compatible = "mediatek,mt7622-snand";
557		reg = <0 0x1100d000 0 0x1000>;
558		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
559		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
560		clock-names = "nfi_clk", "pad_clk";
561		nand-ecc-engine = <&bch>;
562		#address-cells = <1>;
563		#size-cells = <0>;
564		status = "disabled";
565	};
566
567	bch: ecc@1100e000 {
568		compatible = "mediatek,mt7622-ecc";
569		reg = <0 0x1100e000 0 0x1000>;
570		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
571		clocks = <&pericfg CLK_PERI_NFIECC_PD>;
572		clock-names = "nfiecc_clk";
573		status = "disabled";
574	};
575
576	nor_flash: spi@11014000 {
577		compatible = "mediatek,mt7622-nor",
578			     "mediatek,mt8173-nor";
579		reg = <0 0x11014000 0 0xe0>;
580		clocks = <&pericfg CLK_PERI_FLASH_PD>,
581			 <&topckgen CLK_TOP_FLASH_SEL>;
582		clock-names = "spi", "sf";
583		#address-cells = <1>;
584		#size-cells = <0>;
585		status = "disabled";
586	};
587
588	spi1: spi@11016000 {
589		compatible = "mediatek,mt7622-spi";
590		reg = <0 0x11016000 0 0x100>;
591		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
592		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
593			 <&topckgen CLK_TOP_SPI1_SEL>,
594			 <&pericfg CLK_PERI_SPI1_PD>;
595		clock-names = "parent-clk", "sel-clk", "spi-clk";
596		#address-cells = <1>;
597		#size-cells = <0>;
598		status = "disabled";
599	};
600
601	uart4: serial@11019000 {
602		compatible = "mediatek,mt7622-uart",
603			     "mediatek,mt6577-uart";
604		reg = <0 0x11019000 0 0x400>;
605		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
606		clocks = <&topckgen CLK_TOP_UART_SEL>,
607			 <&pericfg CLK_PERI_UART4_PD>;
608		clock-names = "baud", "bus";
609		status = "disabled";
610	};
611
612	audsys: clock-controller@11220000 {
613		compatible = "mediatek,mt7622-audsys", "syscon";
614		reg = <0 0x11220000 0 0x2000>;
615		#clock-cells = <1>;
616
617		afe: audio-controller {
618			compatible = "mediatek,mt7622-audio";
619			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
620				     <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
621			interrupt-names = "afe", "asys";
622
623			clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
624				 <&topckgen CLK_TOP_AUD1_SEL>,
625				 <&topckgen CLK_TOP_AUD2_SEL>,
626				 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
627				 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
628				 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
629				 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
630				 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
631				 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
632				 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
633				 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
634				 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
635				 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
636				 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
637				 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
638				 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
639				 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
640				 <&audsys CLK_AUDIO_I2SO1>,
641				 <&audsys CLK_AUDIO_I2SO2>,
642				 <&audsys CLK_AUDIO_I2SO3>,
643				 <&audsys CLK_AUDIO_I2SO4>,
644				 <&audsys CLK_AUDIO_I2SIN1>,
645				 <&audsys CLK_AUDIO_I2SIN2>,
646				 <&audsys CLK_AUDIO_I2SIN3>,
647				 <&audsys CLK_AUDIO_I2SIN4>,
648				 <&audsys CLK_AUDIO_ASRCO1>,
649				 <&audsys CLK_AUDIO_ASRCO2>,
650				 <&audsys CLK_AUDIO_ASRCO3>,
651				 <&audsys CLK_AUDIO_ASRCO4>,
652				 <&audsys CLK_AUDIO_AFE>,
653				 <&audsys CLK_AUDIO_AFE_CONN>,
654				 <&audsys CLK_AUDIO_A1SYS>,
655				 <&audsys CLK_AUDIO_A2SYS>;
656
657			clock-names = "infra_sys_audio_clk",
658				      "top_audio_mux1_sel",
659				      "top_audio_mux2_sel",
660				      "top_audio_a1sys_hp",
661				      "top_audio_a2sys_hp",
662				      "i2s0_src_sel",
663				      "i2s1_src_sel",
664				      "i2s2_src_sel",
665				      "i2s3_src_sel",
666				      "i2s0_src_div",
667				      "i2s1_src_div",
668				      "i2s2_src_div",
669				      "i2s3_src_div",
670				      "i2s0_mclk_en",
671				      "i2s1_mclk_en",
672				      "i2s2_mclk_en",
673				      "i2s3_mclk_en",
674				      "i2so0_hop_ck",
675				      "i2so1_hop_ck",
676				      "i2so2_hop_ck",
677				      "i2so3_hop_ck",
678				      "i2si0_hop_ck",
679				      "i2si1_hop_ck",
680				      "i2si2_hop_ck",
681				      "i2si3_hop_ck",
682				      "asrc0_out_ck",
683				      "asrc1_out_ck",
684				      "asrc2_out_ck",
685				      "asrc3_out_ck",
686				      "audio_afe_pd",
687				      "audio_afe_conn_pd",
688				      "audio_a1sys_pd",
689				      "audio_a2sys_pd";
690
691			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
692					  <&topckgen CLK_TOP_A2SYS_HP_SEL>,
693					  <&topckgen CLK_TOP_A1SYS_HP_DIV>,
694					  <&topckgen CLK_TOP_A2SYS_HP_DIV>;
695			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
696						 <&topckgen CLK_TOP_AUD2PLL>;
697			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
698		};
699	};
700
701	mmc0: mmc@11230000 {
702		compatible = "mediatek,mt7622-mmc";
703		reg = <0 0x11230000 0 0x1000>;
704		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
705		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
706			 <&topckgen CLK_TOP_MSDC50_0_SEL>;
707		clock-names = "source", "hclk";
708		resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
709		reset-names = "hrst";
710		status = "disabled";
711	};
712
713	mmc1: mmc@11240000 {
714		compatible = "mediatek,mt7622-mmc";
715		reg = <0 0x11240000 0 0x1000>;
716		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
717		clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
718			 <&topckgen CLK_TOP_AXI_SEL>;
719		clock-names = "source", "hclk";
720		resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
721		reset-names = "hrst";
722		status = "disabled";
723	};
724
725	wmac: wmac@18000000 {
726		compatible = "mediatek,mt7622-wmac";
727		reg = <0 0x18000000 0 0x100000>;
728		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
729
730		mediatek,infracfg = <&infracfg>;
731		status = "disabled";
732
733		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
734	};
735
736	ssusbsys: ssusbsys@1a000000 {
737		compatible = "mediatek,mt7622-ssusbsys",
738			     "syscon";
739		reg = <0 0x1a000000 0 0x1000>;
740		#clock-cells = <1>;
741		#reset-cells = <1>;
742	};
743
744	ssusb: usb@1a0c0000 {
745		compatible = "mediatek,mt7622-xhci",
746			     "mediatek,mtk-xhci";
747		reg = <0 0x1a0c0000 0 0x01000>,
748		      <0 0x1a0c4700 0 0x0100>;
749		reg-names = "mac", "ippc";
750		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
751		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
752		clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
753			 <&ssusbsys CLK_SSUSB_REF_EN>,
754			 <&ssusbsys CLK_SSUSB_MCU_EN>,
755			 <&ssusbsys CLK_SSUSB_DMA_EN>;
756		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
757		phys = <&u2port0 PHY_TYPE_USB2>,
758		       <&u3port0 PHY_TYPE_USB3>,
759		       <&u2port1 PHY_TYPE_USB2>;
760
761		status = "disabled";
762	};
763
764	u3phy: t-phy@1a0c4000 {
765		compatible = "mediatek,mt7622-tphy",
766			     "mediatek,generic-tphy-v1";
767		reg = <0 0x1a0c4000 0 0x700>;
768		#address-cells = <2>;
769		#size-cells = <2>;
770		ranges;
771		status = "disabled";
772
773		u2port0: usb-phy@1a0c4800 {
774			reg = <0 0x1a0c4800 0 0x0100>;
775			#phy-cells = <1>;
776			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
777			clock-names = "ref";
778		};
779
780		u3port0: usb-phy@1a0c4900 {
781			reg = <0 0x1a0c4900 0 0x0700>;
782			#phy-cells = <1>;
783			clocks = <&clk25m>;
784			clock-names = "ref";
785		};
786
787		u2port1: usb-phy@1a0c5000 {
788			reg = <0 0x1a0c5000 0 0x0100>;
789			#phy-cells = <1>;
790			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
791			clock-names = "ref";
792		};
793	};
794
795	pciesys: pciesys@1a100800 {
796		compatible = "mediatek,mt7622-pciesys",
797			     "syscon";
798		reg = <0 0x1a100800 0 0x1000>;
799		#clock-cells = <1>;
800		#reset-cells = <1>;
801	};
802
803	pciecfg: pciecfg@1a140000 {
804		compatible = "mediatek,generic-pciecfg", "syscon";
805		reg = <0 0x1a140000 0 0x1000>;
806	};
807
808	pcie0: pcie@1a143000 {
809		compatible = "mediatek,mt7622-pcie";
810		device_type = "pci";
811		reg = <0 0x1a143000 0 0x1000>;
812		reg-names = "port0";
813		linux,pci-domain = <0>;
814		#address-cells = <3>;
815		#size-cells = <2>;
816		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
817		interrupt-names = "pcie_irq";
818		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
819			 <&pciesys CLK_PCIE_P0_AHB_EN>,
820			 <&pciesys CLK_PCIE_P0_AUX_EN>,
821			 <&pciesys CLK_PCIE_P0_AXI_EN>,
822			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
823			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
824		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
825			      "axi_ck0", "obff_ck0", "pipe_ck0";
826
827		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
828		bus-range = <0x00 0xff>;
829		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
830		status = "disabled";
831
832		#interrupt-cells = <1>;
833		interrupt-map-mask = <0 0 0 7>;
834		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
835				<0 0 0 2 &pcie_intc0 1>,
836				<0 0 0 3 &pcie_intc0 2>,
837				<0 0 0 4 &pcie_intc0 3>;
838		pcie_intc0: interrupt-controller {
839			interrupt-controller;
840			#address-cells = <0>;
841			#interrupt-cells = <1>;
842		};
843	};
844
845	pcie1: pcie@1a145000 {
846		compatible = "mediatek,mt7622-pcie";
847		device_type = "pci";
848		reg = <0 0x1a145000 0 0x1000>;
849		reg-names = "port1";
850		linux,pci-domain = <1>;
851		#address-cells = <3>;
852		#size-cells = <2>;
853		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
854		interrupt-names = "pcie_irq";
855		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
856			 /* designer has connect RC1 with p0_ahb clock */
857			 <&pciesys CLK_PCIE_P0_AHB_EN>,
858			 <&pciesys CLK_PCIE_P1_AUX_EN>,
859			 <&pciesys CLK_PCIE_P1_AXI_EN>,
860			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
861			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
862		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
863			      "axi_ck1", "obff_ck1", "pipe_ck1";
864
865		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
866		bus-range = <0x00 0xff>;
867		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
868		status = "disabled";
869
870		#interrupt-cells = <1>;
871		interrupt-map-mask = <0 0 0 7>;
872		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
873				<0 0 0 2 &pcie_intc1 1>,
874				<0 0 0 3 &pcie_intc1 2>,
875				<0 0 0 4 &pcie_intc1 3>;
876		pcie_intc1: interrupt-controller {
877			interrupt-controller;
878			#address-cells = <0>;
879			#interrupt-cells = <1>;
880		};
881	};
882
883	sata: sata@1a200000 {
884		compatible = "mediatek,mt7622-ahci",
885			     "mediatek,mtk-ahci";
886		reg = <0 0x1a200000 0 0x1100>;
887		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
888		interrupt-names = "hostc";
889		clocks = <&pciesys CLK_SATA_AHB_EN>,
890			 <&pciesys CLK_SATA_AXI_EN>,
891			 <&pciesys CLK_SATA_ASIC_EN>,
892			 <&pciesys CLK_SATA_RBC_EN>,
893			 <&pciesys CLK_SATA_PM_EN>;
894		clock-names = "ahb", "axi", "asic", "rbc", "pm";
895		phys = <&sata_port PHY_TYPE_SATA>;
896		phy-names = "sata-phy";
897		ports-implemented = <0x1>;
898		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
899		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
900			 <&pciesys MT7622_SATA_PHY_SW_RST>,
901			 <&pciesys MT7622_SATA_PHY_REG_RST>;
902		reset-names = "axi", "sw", "reg";
903		mediatek,phy-mode = <&pciesys>;
904		status = "disabled";
905	};
906
907	sata_phy: t-phy@1a243000 {
908		compatible = "mediatek,mt7622-tphy",
909			     "mediatek,generic-tphy-v1";
910		#address-cells = <2>;
911		#size-cells = <2>;
912		ranges;
913		status = "disabled";
914
915		sata_port: sata-phy@1a243000 {
916			reg = <0 0x1a243000 0 0x0100>;
917			clocks = <&topckgen CLK_TOP_ETH_500M>;
918			clock-names = "ref";
919			#phy-cells = <1>;
920		};
921	};
922
923	hifsys: syscon@1af00000 {
924		compatible = "mediatek,mt7622-hifsys", "syscon";
925		reg = <0 0x1af00000 0 0x70>;
926	};
927
928	ethsys: syscon@1b000000 {
929		compatible = "mediatek,mt7622-ethsys",
930			     "syscon";
931		reg = <0 0x1b000000 0 0x1000>;
932		#clock-cells = <1>;
933		#reset-cells = <1>;
934	};
935
936	hsdma: dma-controller@1b007000 {
937		compatible = "mediatek,mt7622-hsdma";
938		reg = <0 0x1b007000 0 0x1000>;
939		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
940		clocks = <&ethsys CLK_ETH_HSDMA_EN>;
941		clock-names = "hsdma";
942		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
943		#dma-cells = <1>;
944		dma-requests = <3>;
945	};
946
947	pcie_mirror: pcie-mirror@10000400 {
948		compatible = "mediatek,mt7622-pcie-mirror",
949			     "syscon";
950		reg = <0 0x10000400 0 0x10>;
951	};
952
953	wed0: wed@1020a000 {
954		compatible = "mediatek,mt7622-wed",
955			     "syscon";
956		reg = <0 0x1020a000 0 0x1000>;
957		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
958	};
959
960	wed1: wed@1020b000 {
961		compatible = "mediatek,mt7622-wed",
962			     "syscon";
963		reg = <0 0x1020b000 0 0x1000>;
964		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
965	};
966
967	eth: ethernet@1b100000 {
968		compatible = "mediatek,mt7622-eth",
969			     "mediatek,mt2701-eth",
970			     "syscon";
971		reg = <0 0x1b100000 0 0x20000>;
972		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
973			     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
974			     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
975		clocks = <&topckgen CLK_TOP_ETH_SEL>,
976			 <&ethsys CLK_ETH_ESW_EN>,
977			 <&ethsys CLK_ETH_GP0_EN>,
978			 <&ethsys CLK_ETH_GP1_EN>,
979			 <&ethsys CLK_ETH_GP2_EN>,
980			 <&sgmiisys CLK_SGMII_TX250M_EN>,
981			 <&sgmiisys CLK_SGMII_RX250M_EN>,
982			 <&sgmiisys CLK_SGMII_CDR_REF>,
983			 <&sgmiisys CLK_SGMII_CDR_FB>,
984			 <&topckgen CLK_TOP_SGMIIPLL>,
985			 <&apmixedsys CLK_APMIXED_ETH2PLL>;
986		clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
987			      "sgmii_tx250m", "sgmii_rx250m",
988			      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
989			      "eth2pll";
990		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
991		mediatek,ethsys = <&ethsys>;
992		mediatek,sgmiisys = <&sgmiisys>;
993		cci-control-port = <&cci_control2>;
994		mediatek,wed = <&wed0>, <&wed1>;
995		mediatek,pcie-mirror = <&pcie_mirror>;
996		mediatek,hifsys = <&hifsys>;
997		dma-coherent;
998		#address-cells = <1>;
999		#size-cells = <0>;
1000		status = "disabled";
1001	};
1002
1003	sgmiisys: sgmiisys@1b128000 {
1004		compatible = "mediatek,mt7622-sgmiisys",
1005			     "syscon";
1006		reg = <0 0x1b128000 0 0x3000>;
1007		#clock-cells = <1>;
1008	};
1009};
1010